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AR# 61934

MIG v3.92 Spartan-6 DDR2/DDR3 - When I share PLL in mutiple MIG cores, only one BUFPLL_MCB is locked.

Description

On large Spartan-6 package devices, there are up to 4 MCBs that can work at the same time. 

Generally, one PLL is required to drive MCBs in the same side. 

To save PLL resources, when MCBs in different sides work at the same frequency, PLL can be shared. 

When I share the PLL for two MCBs, BUFPLL_MCB at the right side doesn't lock if the PLL_ADV location is PLL_ADV_X0Y2.  

However the single MCB design with same MCB location works fine.  

 Shared PLL Design :
 PLL_ADV LOC : PLL_ADV_X0Y0
 BUFPLL_MCB1 : BUFPLL_MCB_X2Y5 locked
 BUFPLL_MCB2 : BUFPLL_MCB_X0Y5 locked

 Shared PLL Design :
 PLL_ADV LOC : PLL_ADV_X0Y2
 BUFPLL_MCB1 : BUFPLL_MCB_X2Y5 not locked 
 BUFPLL_MCB2 : BUFPLL_MCB_X0Y5 locked

 

Solution

The root cause is that the connection between output of PLL_ADV to input of the unlocked BUFPLL_MCB doesn't use the most optimized routing. 

This issue can be worked around by following the steps below:

 

Step 1

Generate a single MCB design, create a DIRT routing for the net driven to BUFPLL_MCB_X2Y5.

This can be done in FPGA editor.


Find the net inside FPGA editor, select it, then invoke: tools->directed routing constraints and allow it to create the DIRT strings for these two nets:
 

fpga_dirt.gif


 
The generated constraints will be appended to the UCF file.

 


Step 2

Use the DIRT routing constraint for the current design, it will keep the same routing.

This DIRT constraint will force the net on to the same connection as in the other design.

 

Revision History:

9/10/2014 - Initial Release

AR# 61934
Date Created 09/05/2014
Last Updated 01/05/2016
Status Active
Type General Article
Devices
  • Spartan-6 LX
Tools
  • ISE
IP
  • MIG Virtex-6 and Spartan-6