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AR# 61970

v2.0 - AXI IIC – AXI IIC example configured for SCL of 100 KHz derives a lesser frequency


We are trying to simulate an AXI IIC example design generated by Vivado.

We have configured AXI IIC for a Serial Clock (SCL) of 100 KHz.

However the SCL clock measured by simulation is less than 100 KHz.

How can we fix this issue?


This is an expected behavior with the AXI IIC controller.

However there are no functional issues seen using this core on board.

For an AXI IIC configured with an AXI Interconnect Clock of 25MHz and a SCL configured with 100KHz with no-inertial delays, make the following changes:

(The following parameters will have a default value of 122)

TLOW should be changed to 118
THIGH should be changed to 118
Once this is set in the core, the SCL frequency should be 99.6 KHz
AR# 61970
Date 09/16/2014
Status Active
Type Known Issues
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • AXI IIC Bus Interface