AR# 61994


vivado 2014.2 Accumulator v12.0 ; Accumulator HDL Netlist simulation does not behave the same when implementing in fabric and dsp48


The behavior of the Bypass (Load) input relative to Clock Enable (CE) is different for the fabric and DSP48 implementations of the Accumulator.

In the fabric implementation, Bypass overrides CE, so the Accumulator can be loaded even when CE is Low.

In the DSP48 implementation, CE overrides Bypass, and as such CE must be High in order to load the Accumulator.

If Bypass and CE are both required, it is therefore not possible to change seamlessly between fabric and DSP48 implementations.


This is a known issue with Accumulator v11.0 and Accumulator v12.0

Core versions affected: v11.0, v12.0
Software affected: Vivado, ISE, System Generator for DSP
Simulators affected: All supported simulators

One workaround is to AND the Bypass and Clock Enable signals external to the fabric implementation to generate a new Bypass signal which will behave in the same way as the DSP48 implementation. 

The resource and timing impact of this workaround is negligible.

Currently there is no workaround to make the DSP48 implementation Bypass behavior the same as the fabric implementation.

AR# 61994
Date 10/13/2014
Status Active
Type General Article
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