AR# 62018

Video IP - TIMING #1 Warning regarding missing ASYNC_REG attribute on synchronizer


When using various video IP, I am receiving the following DRC warnings during timing analysis:

TIMING #1 Warning A logic synchronizer U0/obsakpqmiigu5yepkpsm2p/obsfcuxzipbqcmj4btruj4jaauj4irag with double-registers has been detected between clock aclk and clock m_axi_aclk but the synchronizer does not have the property ASYNC_REG defined 
TIMING #2 Warning A logic synchronizer U0/obsakpqmiigu5yepkpsm2p/obsicuxzipbqcmj4btruj4gbcmb4irag with double-registers has been detected between clock aclk and clock m_axi_aclk but the synchronizer does not have the property ASYNC_REG defined 


This is a known limitation currently affecting a number of IP.

This does not affect functionality of any IP, but can affect simulation and/or timing quality of results for a given implementation.

Referring to the 'Vivado Properties Reference' guide (UG912):

ASYNC_REG is an attribute that affects many processes in the Vivado tools flow. ASYNC_REG
specifies that:
A register can receive asynchronous data on the D input pin relative to its source clock.
The register is a synchronizing register within a synchronization chain.
During simulation, when a timing violation occurs, the default behavior is for a register
element to output an 'X', or unknown state (not a 1 or 0). When this happens, anything that
element drives will see an 'X' on its input and in turn enters an unknown state. This
condition can propagate through the design, in some cases causing large sections of the
design to become unknown, and sometimes the simulator can not recover from this state.
ASYNC_REG modifies the register to output the last known value even though a timing
violation occurs.

The Vivado synthesis, when encountering this attribute treats it as a DONT_TOUCH attribute
and pushes the ASYNC_REG property forward in the netlist. This ensures that synthesis will
not optimize registers or surrounding logic, and that tools later in the flow receive the
property to handle it correctly.

Specifying ASYNC_REG also affects optimization, placement, and routing to improve Mean
Time Between Failure (MTBF) for registers that may go metastable. If ASYNC_REG is applied,
the placer will ensure the flip-flops on a synchronization chain are placed closely to
maximize MTBF. Registers with ASYNC_REG that are directly connected will be grouped and
placed together into a single SLICE, assuming they have a compatible control set and the
number of registers does not exceed the available resources of the SLICE.

This can be worked around by manually applying the ASYNC_REG attribute to the cells in question using XDC constraints:

set_property ASYNC_REG TRUE [get_cells instance_name]

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56854 Xilinx Multimedia, Video and Imaging Solution Center - Documentation N/A N/A
AR# 62018
Date 09/12/2014
Status Active
Type General Article