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AR# 62042

Zynq-7000 AP SoC, Vivado 2014.2 - PS DDRC asserts ODT during reads


In Vivado versions 2014.2 and earlier, during DDR3/3L reads to DRAM, the Zynq PS DDRC will assert the ODT signal during reads.

It is approximately a one cycle pulse width, asserted twice in a read command.



A write of 0 to bit [0] of DRAM_ODT_reg (0xF8006048) will prevent this behavior.

This can be done by editing the ps7_init.tcl and ps7_init.c files, enabling the write mask to actually clear the bit (which is enabled in silicon by default).
For example, change the line below in ps7_init.c from:

EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),


EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),

The value of 0x8 represents the silicon default of '1' in bit [3], making it more explicit and matches the fix in later software versions.

This issue is fixed in Vivado 2014.3.
AR# 62042
Date 11/04/2014
Status Active
Type General Article
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2013.4
  • More
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.2
  • Less