AR# 62049


2014.2 - Vivado Logic Debug - ERROR: [Place 30-188] UnBuffered I/O's


In non-project mode, when the ILA is synthesized in OOC mode, the synthesized design does not include the OBUF.

FDRE output is directly connected to the output port without any OBUF.
As a result, place_design fails with the following Error:

ERROR: [Place 30-188] UnBuffered IOs: dout has following unbuffered src : count_reg[7](FDRE)
ERROR: [Place 30-389] IO port 'dout' does not have an associated buffer


To work around this issue use the non-OOC flow.

This issue is fixed in the 2014.3 release of Vivado.
AR# 62049
Date 09/26/2014
Status Active
Type General Article
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