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AR# 62050

UltraScale DDR4/DDR3 - Can reset_n be allocated to an I/O or does it have to be within a memory interface bank?

Description

Version Found: DDR4 v5.0, DDR3 v5.0

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

The LogiCORE IP Architecture UltraScale Based FPGAs Memory Interface Solutions (PG150) currently states the following pin rule for DDR4/DDR3:


"* reset_n can only be allocated within the memory interface banks"
 

Previous MIG generations allowed the reset_n pin to be placed anywhere within the FPGA as long as timing was met.

Why has this changed?

Solution

This limitation on reset_n will be lifted in a future release. 

The same rule of allowing reset_n to be allocated to any FPGA pin so long as timing is met will be supported. 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 62050
Date 12/21/2017
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale
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