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AR# 62055

MIG Ultrascale DDR4/3 - MIG incorrectly allows Data Mask (DM) to be disabled for AXI designs


Version Found: v5.0
Version Resolved: See (Xilinx Answer 58435)


The AXI option is disabled in the MIG GUI when x4 memory parts are chosen.

The Data Mask option is disabled for memory interfaces that have x4 parts.

Because AXI addressing is Byte-wise and it can do un-aligned address transactions, Data Mask is always needed.

This issue affects the Vivado IP catalog and IPI designs.


A future workaround for this issue will to be use Read-Modified Writes. 

This workaround will be added into the MIG code in a future release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 62055
Date 10/08/2014
Status Active
Type General Article
  • Virtex UltraScale
  • Kintex UltraScale
  • MIG UltraScale
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