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  1. Xilinx - All Programmable
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  3. AR# 62062: 2014.2 AXI Traffic Generator: IRQ signal is not generated when either write/read cycle is completed and Loopback is disabled at the same time

AR# 62062

2014.2 AXI Traffic Generator: IRQ signal is not generated when either write/read cycle is completed and Loopback is disabled at the same time

Description

AXI Traffic generator fails to generate an IRQ signal when either the write or read cycle is completed and Loopback is disabled at the same time.

Solution

This is a known issue which is fixed in the 2014.3 release of Vivado Design Suite.
AR# 62062
Date 10/01/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2014.2
IP
  • AXI Traffic Generator