Description

Version Found: 1.0

Version Resolved and other known issues: (Xilinx Answer 61898)

I am running the AXI Bridge for PCI Express Gen3 v1.0 core example design simulation using QuestaSim 10.3b.

The simulator errors out during the compilation phase with the following error:

-----------------------------
# Top level modules:
# End time: 12:37:42 on Jul 31,2014, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# QuestaSim-64 vlog 10.3b Compiler 2014.05 May 29 2014
# Start time: 12:37:42 on Jul 31,2014
# vlog -incr -work axi_pcie3_v1_0 ./../../../axi_pcie3_0_example.srcs/sources_1/ip/axi_pcie3_0/axi_pcie3_v1_0/hdl/verilog/axi_pcie_v2_3_axi_enhanced_cfg_slave.v "+incdir+./../../../axi_pcie3_0_example.srcs/sources_1/ip/axi_pcie3_0/axi_pcie3_v1_0/hdl/verilog" "+incdir+./../../../axi_pcie3_0_example.srcs/sim_1/imports/simulation/functional" "+incdir+./../../../axi_pcie3_0_example.srcs/sim_1/imports/simulation/dsport" "+incdir+./../../../axi_pcie3_0_example.srcs/sim_1/imports/simulation/tests"
# SIGABRT: SIGABRT
# ** Error: /tools/gensys/questa/10

Solution

This issue occurs due to a problem in the simulator.

To resolve the issue, please use QuestaSim 10.3c_1

Note: "Version Found" refers to the version the problem was first discovered.

The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

10/02/2014 - Initial Release