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AR# 62073

Vivado Synthesis - Optimization causes CARRY4 inputs to be connected incorrectly

Description

In a Vivado 2014.2 design that uses carry chains, and where the first CARRY4 instance of a carry chain is optimized due to a constant being propagated, the carry logic that is inferred can result in incorrect functionality.

This is due to the input ports being connected incorrectly. 

This is usually seen later in the flow when the following DRC is reported: 

REQP-1745#1 Advisory
connects_CI_VCC_connects_CYINIT_GND
The CARRY4 cell
top/sub1/sub2/test_reg_i_3
has CI tied to VCC and CYINIT tied to GND. The CYINIT connection to GND will take precedence.
Related violations: <none>

 

How can this be avoided?

Solution

The issue is a regression from 2013.3 and first appeared in the 2013.4 Vivado release.


This problem is due to an optimization of constant logic during synthesis. 

While removing a redundant instance of a carry chain, the connectivity is changed. 


In the elaborated design, the CI and CYINIT have the following correct connections:

CI <= GND
CYINIT <= VCC

 
However, after synthesis, the connectivity changes:

CI <= VCC
CYINIT <= GND
 
CR_problem_connection.png

 
Since this is the first CARRY4 instance in a chain, the CYINIT is used to determine the add/subtract functionality.

Moving the VCC from CYINIT to CI changes the functionality and causes the problem.
 
This has been fixed for the 2014.3 version of Vivado.

To work around this in 2013.4, 2014.1 and 2014.2, use the following parameter:
 
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter constPropCarry false"
AR# 62073
Date Created 09/17/2014
Last Updated 10/08/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2013.4