In a Vivado 2014.2 design that uses carry chains, and where the first CARRY4 instance of a carry chain is optimized due to a constant being propagated, the carry logic that is inferred can result in incorrect functionality.
This is due to the input ports being connected incorrectly.
This is usually seen later in the flow when the following DRC is reported:
How can this be avoided?
The issue is a regression from 2013.3 and first appeared in the 2013.4 Vivado release.
This problem is due to an optimization of constant logic during synthesis.
While removing a redundant instance of a carry chain, the connectivity is changed.
In the elaborated design, the CI and CYINIT have the following correct connections:
However, after synthesis, the connectivity changes:
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter constPropCarry false"