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  1. Xilinx - All Programmable
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  3. AR# 62086: MIG UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mapping

AR# 62086

MIG UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mapping

Description

Version Found: v5.0 Rev1
Version Resolved: See (Xilinx Answer 58435)
 
The Performance Traffic Generator is only set up to work with the default Memory Address Map setting of "BANK ROW COLUMN".

The performance_sim.do will still run if a different address mapping scheme is used, but results will not be accurate and it will yield low efficiency results.

Solution

This is only an issue with the Performance Traffic Generator and not with the MIG UltraScale IP as the address mapping is correctly implemented in the core and in hardware. 

The Performance Traffic Generator will be updated to support all Memory Address Map settings in a future release.

Revision History
10/27/2014 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 62086
Date 11/05/2014
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale