UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 62087: IP Soft Error Mitigation 7-series status_heartbeat specification

AR# 62087

IP Soft Error Mitigation 7-series status_heartbeat specification

Description

Status_heartbeat pulse may lag more than the 128 cycles specified in PG036.

The PG036 specification on 7series SEM IP status_heartbeat is incorrect.
 

Table 2-17 in PG036 indicates that the status_heartbeat will pulse at least once every 128 clock cycles.

This specification of 128 clock cycles is incorrect for 7series SEM IP.

Solution

At the end of an FPGA device scan address, status_heartbeat can be higher than the specified 128 cycles, up to 150 cycles.

 

As soon as the next set of device scans start from the top of the device it will assert within 128 cycles, so systems that monitor status_heartbeat do not need to alarm unless status_heartbeat is delayed more than 150 cycles.

 

This change is only applicable for 7 series and does not apply to Spartan-6 or Virtex-6 SEM IP. 


PG036 will be updated with the correct number.

 

 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54642 Soft Error Mitigation IP Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 62087
Date 10/16/2014
Status Active
Type General Article
Devices
IP
Page Bookmarked