We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62092

Vivado Sysgen - Fast Fourier Transform 9.0 C-model not simulating correctly in Sysgen for all cases


My Sysgen Simulation shows different outputs from the Fast Fourier Transform core than when it is running on Hardware.

The HDL Netlist project simulated in Vivado produces the same results as in Hardware.

Why does my Sysgen simulation appear to be different?

Is there a workaround for this issue?


This is likely due to a limitation in the C Model which is used when simulating the Fast Fourier Transform core in Vivado Sysgen.

If the OVFL output is enabled for the core and is asserted during the simulation, the data should be ignored.

The following extract is from the FFT 9.0 C Model section of the Product Guide.


Prior to Vivado 2014.3, it is not possible to work around this issue.

From the 2014.3 release on, it is possible to configure Sysgen to use HDL Simulation models for the FFT core instead of the C Model to work around this issue.

AR# 62092
Date 01/19/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.1
  • System Generator for DSP
  • Fast Fourier Transform
Page Bookmarked