When analyzing the clock network, in some designs Vivado shows LUT primitive buffers for my clocks:
In some cases, the input of the register is shown in the clock network report:
Is this expected behavior of the clock networks report?
"report_clock_networks" traces down every clock in design.
A clock is a signal that drives either the G-input of a latch or the clock inputs of sequential elements like registers, block RAMs and DSPs.
As soon as a signal is identified as a clock, it will show the entire tree of that signal from the source to all of the loads, including the non-sequential elements like LUTs.
An improvement is planned to add a filter in the clock networks report and only show the sequential elements.
The clock networks report shows the real situation of the design.
If the clock is buffered by a LUT, this will be shown in the clock networks report.