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AR# 62140

7 Series FPGAs Transceiver Wizard v3.4 - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the 7 series FPGAs Transceiver Wizard v3.4 released with the Vivado 2014.3 design tool.

Solution

Known Issues and Release Notes
 
 
Issue 1:
 
Selecting REFCLK as the source for TX/RXOUTCLK gives pulse width violations on TX/RXOUTCLK.
 
Solution: 
 
Select REFCLK as the source of TX/RXOUTCLK, when REFCLK is within the permitted range of TX/RXOUTCLK.
If the REFCLK frequency is outside of the range of TXOUTCLK, use the TXPLLREFCLK_DIV2 option.
 
7 series device data sheets provides the frequency range of these clocks.
 
Artix-7 GTP: DS181 - Table 54
Kintex-7 GTX: Ds182: Table 60
Virtex-7GTX/GTH: DS183: Table 57,Table 72

 


Issue 2:

Invalid Configurations are selectable in the GTZ wizard GUI.

Solution:

Try to ensure that the TXUSERCLK and RXUSERCLK of GTZ are equal.
Select MULTI LANE MODE only if all of the GTZ transceivers are configured identically, otherwise select OFF for Multi Lane mode.
The Wizard gives options to incorrectly select different TXUSERCLK and RXUSERCLK configurations which will result in data loss.
 
Example of Invalid Configuration:
 
CHANNEL0 :   TX Line rate   25.78125    RXlinerate25.78125    REFCLK Source : REFCLK0
TXUSERCLK_SEL_LANE : TXUSRCLK0
RXUSERCLK_SEL_LANE : RXUSRCLK0
 
CHANNEL1:    TX Line rate  -- 3.45             RX Line rate  -- 3.45         REFCLK Source  : REFCLK1
TXUSERCLK_SEL_LANE : TXUSRCLK1
RXUSERCLK_SEL_LANE : RXUSRCLK1
TXUSERCLK0 Source: OCTAL0_TXOUCLK0
RXUSERCLK0 Source: OCTAL0_TXOUCLK0
TXUSERCLK1 Source: OCTAL0_TXOUCLK1
RXUSERCLK1 Source: OCTAL0_TXOUCLK1
TXOUTCLK0 Selection: TXOUTCLK_LANE1
RXOUTCLK0 Selection: TXOUTCLK_LANE1
TXOUTCLK1 Selection: TXOUTCLK_LANE0
RXOUTCLK1 Selection: TXOUTCLK_LANE0
 
In this selection the TXOUTCLK of CHANNEL0 is becoming the source for the TXUSERCLK of CHANNEL1 and hence the configuration is invalid.

 


Issue3:

A CDC issue is seen in RX STARTUP FSM for VHDL designs targeting 7-series GTH and GTP transceivers.

Solution:

Change the following code:

sync_txpmaresetdone: <component_name>_sync_block
Port_map
                (
                     clk               =>   STABLE_CLOCK,
                     data_in       =>   TXPMARESETDONE,
                     data_out    =>   txpmaresetdone_s
                 );
 
To
 
sync_txpmaresetdone: <component_name>_sync_block
Port_map
                (
      
               clk               =>   TXOUTCLK
                     data_in       =>   TXPMARESETDONE,
                     data_out    =>   txpmaresetdone_s
                 );

 


Issue 4:

Incorrect Channel Bonding Daisy chain for lanes greater than 7 for 4 byte internal data path.
 
Solution:
Currently, for 8 lane channel bonded designs, the wizard outputs daisy chaining in the below manner:
channelbond1.jpg

Here the master lane gets RXCHANBONDLEVEL as 4 which is invalid for a 4 byte internal data path.
One solution for this issue can be found below.
As a general solution, try to do daisy chaining so that the master RXCHANBONDLEVEL is   <=3 .
 
 
channelbond2.jpg




 

Issue 5: Optimization of CPLL railing logic

Solution:

The GT wizard wrapper instantiates CPLL railing logic in  the <component_name>_gtx.v file. 

When the same REFCLK is used for multiple GTs, the logic could get duplicated.

Please find the attached modules (cpll_railing.v, sync_block.v) for the CPLL railing logic.

Instantiate it in multi-gt wrapper level for each REFCLK used.

Once this has been done, CPLL railing logic is only implemented once for each REFCLK present in the design.
 
Please refer to (Xilinx Answer 59294) for more details about CPLL railing logic.

 
Issue 6: Observed DRC violation:

ERROR: [Drc 23-20] Rule violation (REQP-48) must_use_ref_clock - GTPE2_COMMON cell GT_RX/inst/common0_i/gtpe2_common_i: An input reference clock pin must be used. in Artix 7 designs

 
Solution:
The issue occurs when the clock coming from IBUFDS_GTE2 is not connected to the common module.

Please ensure that the clock coming from IBUFDS_GTE2 is connected to the GTPE2_COMMON module.

 
Issue 7:  QPLL_CFG is not set correctly when TX and RX are using CPLL and QPLL

Solution: 
 
 
When TX is set to a line rate less than 8 Gbps with CPLL and RX set to a line rate greater than 8Gbps with QPLL, QPLL_CFG in the common wrapper is set to 27'h06801C1 (bit[6]=1=QPLL lower band).

However, this is incorrect.

QPLL should be set to upper band 27'h0680181 (bit[6]=0) .
 
 

Revision History:
10/15/2014 - Initial Release

 

Attachments

Associated Attachments

Name File Size File Type
sync_block.v 1 KB V
cpll_railing.v 3 KB V
AR# 62140
Date Created 09/22/2014
Last Updated 11/06/2014
Status Active
Type Release Notes
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • 7 Series FPGAs Transceivers Wizard