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AR# 62144

2014.3 Vivado IP Release Notes - All IP Change Log Information

Description

This answer record contains a comprehensive list of IP change log information from Vivado 2014.3 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

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100G Ethernet (1.3)
 * Version 1.3
 * GT Group selection in GUI tab-3
 * Auto filling of best possible GT locations for the selected CMAC core and GT Group in GUI tab-3
 * Licensing the CMAC core
 * FCS Support
 * 1588 2-Step Ordinary Clock Support
32-bit Initiator/Target for PCI (7-Series) (5.0)
 * Version 5.0 (Rev. 5)
 * Added support for Artix7 Defense grade devices
3GPP LTE Channel Estimator (2.0)
 * Version 2.0 (Rev. 6)
 * Synthesis warning reduction, no functional changes
3GPP LTE MIMO Decoder (3.0)
 * Version 3.0 (Rev. 6)
 * Synthesis warning reduction, no functional changes
 * Corrected C model smoke test return code to 0 for successful completion, no functional changes to the compiled C model
3GPP LTE MIMO Encoder (4.0)
 * Version 4.0 (Rev. 5)
 * No changes
3GPP Mixed Mode Turbo Decoder (2.0)
 * Version 2.0 (Rev. 6)
 * Implemented workaround for segmentation fault seen when simulating with Synopsys VCS-MX
3GPP Turbo Encoder (5.0)
 * Version 5.0 (Rev. 5)
 * Synthesis warning reduction, no functional changes
3GPPLTE Turbo Encoder (4.0)
 * Version 4.0 (Rev. 5)
 * Synthesis warning reduction, no functional changes
64-bit Initiator/Target for PCI (7-Series) (5.0)
 * Version 5.0 (Rev. 5)
 * Added support for Artix7 Defense grade devices
7 Series FPGAs Transceivers Wizard (3.4)
 * Version 3.4
 * Production updates to GTZ
 * Added SATA template for GTX and GTP
 * Removed logic to keep QPLL in powerdown till reference clock is available
 * Removed PCIE template
7 Series Integrated Block for PCI Express (3.0)
 * Version 3.0 (Rev. 3)
 * Enabled PIPE Sim support for Root Port configuration
 * Added support for Kintex7 Low voltage (0.9v) variants, for only Gen1 speed
 * Added support for Kintex7 Defense grade Low voltage (0.9v) variants, for only Gen1 speed
 * Fixed CPLL Power spike on power up issue (AR59294)
AHB-Lite to AXI Bridge (3.0)
 * Version 3.0 (Rev. 2)
 * Repackaged to improve internal automation, no functional changes
 * modified to use new sub-cores in place of proc_common. No functional changes.
AXI 10G-Ethernet Subsystem (2.0)
 * Version 2.0
 * The core is now available in the Vivado IP catalog in addition to the IP integrator tool.
 * 10GBASE-R permutations are now available with or without 1588 timestamping support.
 * Added 10GBASE-KR options.
 * Added MAC Management I/F and Priority Flow Control options.
 * Added GUI option to include or exclude shareable logic resources in the core. There are port changes on the core as a result.
 * Added optional transceiver control and status ports.
 * Added optional transceiver DRP ports.
 * Added example design.
 * Added demonstration testbench.
 * Added UltraScale Pre-Production support to all none 1588 permutations.
 * Added support for Zync-7000 and 7-Series Defense-grade parts
 * Supported 7-Series parts are now at Production status.
 * Increased the accuracy of the hardware timestamps for IEEE1588 support.
 * Updated the default value of the 1588 Transmitted Timestamp Adjustment Control Register: the latency adjust value is now set appropriately to adjust the timestamp point to the edge of the device, and the timestamp correction is now enabled by default.
 * Updated the default value of the 1588 RX Fixed Latency MDIO register: the latency adjust value is now set appropriately to adjust the timestamp point to the edge of the device.
 * Input port default tie-off values for IP Integrator have been added to signal_detect and tx_fault and changed to logic 1 for reset_counter_done, tx_axis_aresetn and rx_axis_aresetn
AXI AHBLite Bridge (3.0)
 * Version 3.0 (Rev. 2)
 * modified to use new sub-cores in place of proc_common. No functional changes.
AXI APB Bridge (3.0)
 * Version 3.0 (Rev. 2)
 * Repackaged to improve internal automation, no functional changes.
 * pselect_f and counter_f are delivered as a part of IP instead of using from proc_common sub-core.
AXI BFM Cores (5.0)
 * Version 5.0 (Rev. 4)
 * Instance name in the hdl file has been modified to make it unique, no functional changes.
 * Updated the default values for input ports
 * Increased the address width parameter range.
 * All the runtime parameters are also made available from GUI.
 * TKEEP and TSTRB ports are made optional.
AXI BRAM Controller (4.0)
 * Version 4.0 (Rev. 2)
 * Re-Packaged to improve internal automation, no functional changes
AXI CAN (5.0)
 * Version 5.0 (Rev. 6)
 * CAN modified to use new sub-cores in place of proc_common. no functional changes
 * Repackaged to map interrupt port to interrupt interface,no functional changes
 * Repackaged to correct exported_name usage,no functional changes
 * BRAM instance depth corrected for UltraScale devices, no functional changes
AXI Central Direct Memory Access (4.1)
 * Version 4.1 (Rev. 4)
 * AXI CDMA modified to use new sub-cores in place of proc_common
 * No functional changes
AXI Chip2Chip Bridge (4.2)
 * Version 4.2 (Rev. 2)
 * Added 12 bit ID Width support on AXI Interfaces
 * Added beta support for optional Aurora 8B10B interface
AXI Clock Converter (2.1)
 * Version 2.1 (Rev. 2)
 * No changes
AXI Crossbar (2.1)
 * Version 2.1 (Rev. 4)
 * Improved automation of Mmm_Sss_READ_CONNECTIVITY and Mmm_Sss_WRITE_CONNECTIVITY parameters in IPI.
AXI Data FIFO (2.1)
 * Version 2.1 (Rev. 2)
 * No changes
AXI Data Width Converter (2.1)
 * Version 2.1 (Rev. 3)
 * Eliminated unnecessary stalling of m_axi_arvalid output due to ID changes under some conditions. IP now supports propagating multiple outstanding transactions regardless of ID value, as stated in the Product Guide.
 * Removed extraneous combinatorial pathway from m_axi_bvalid to m_axi_bready in downsizer configuration.
 * Warning reduction in downsizer configuration.
 * Updated configuration GUI to show transaction splitting information when downsizing
AXI DataMover (5.1)
 * Version 5.1 (Rev. 4)
 * AXI Datamover modified to use new sub-cores in place of proc_common
 * GUI updated to fix propagation/update of MM2S and S2MM DRE parameters
 * No functional changes
AXI Direct Memory Access (7.1)
 * Version 7.1 (Rev. 4)
 * AXI DMA modified to use new sub-cores in place of proc_common
 * Repackaged to improve internal automation
 * No functional changes
AXI EMC (3.0)
 * Version 3.0 (Rev. 2)
 * Improve efficiency of Board flow support
 * modified to use new sub-cores in place of proc_common. No functional changes.
 * Updating core to use utils.tcl needed for board flow from common location.
AXI EPC (2.0)
 * Version 2.0 (Rev. 6)
 * Modified to use new sub-cores in place of proc_common, no functional changes
AXI Ethernet Buffer (2.0)
 * Version 2.0 (Rev. 5)
 * Reduced XDC warnings.
 * Updated to use new subcores in place of proc_common
AXI Ethernet Clocking (2.0)
 * Version 2.0 (Rev. 1)
 * No changes
AXI Ethernet Subsystem (6.2)
 * Version 6.2
 * Support core in native Vivado catalog.
 * Added example design.
 * Added demonstration testbench.
 * Added non Processor Mode.
 * Added Priority Flow Control (PFC) support in non-processor mode.
 * Added 1588 support for UltraScale devices.
 * Support optional Transceiver control and status ports in non-processor mode.
AXI EthernetLite (3.0)
 * Version 3.0 (Rev. 2)
 * IP XDC update for timing DRC, no functional changes.
 * Clock Inversion in IP top removed for timing DRC, no functional changes.
 * modified to use new sub-cores in place of proc_common. No Functional changes.
 * Updating core to use utils.tcl needed for board flow from common location.
AXI GPIO (2.0)
 * Version 2.0 (Rev. 6)
 * Example design updated to have ATG mask change dynamically based on GPIO widths.
 * AXI GPIO uses new libraries and axi_lite_ipif subcores.
 * Updating core to use utils.tcl needed for board flow from common location.
 * Disabling customization of the appropriate GPIO if board interface has been used.
AXI HWICAP (3.0)
 * Version 3.0 (Rev. 6)
 * axi hwicap is modified to use new sub-cores in place of proc_common. No functional changes.
 * GUI is updated to prevent an invalid combination of parameters, no functional changes.
AXI IIC (2.0)
 * Version 2.0 (Rev. 6)
 * AXI IIC uses new lib and axi_lite_ipif libraries
 * soft_reset and srl_fifo are delivered as part of the IP, no functional changes
 * Support added to set default values on GPO port
 * Updating core to use utils.tcl needed for board flow from common location.
AXI Interconnect (2.1)
 * Version 2.1 (Rev. 4)
 * Improved support for automatic register slice placement.
AXI Interrupt Controller (4.1)
 * Version 4.1 (Rev. 2)
 * Updated subcore references, no functional changes
AXI Lite IPIF (3.0)
 * Version 3.0
 * 2014.3 release
 * No longer uses proc_common
 * No functional changes
AXI MMU (2.1)
 * Version 2.1 (Rev. 1)
 * Internal flow changes only; no user-visible changes.
AXI Master Burst (2.0)
 * Version 2.0 (Rev. 5)
 * Updated the RTL to use new sub-cores in place of proc_common,no functional changes.
AXI Memory Mapped To Gen3 PCI Express (1.0)
 * Version 1.0
 * Initial release
AXI Memory Mapped To PCI Express (2.5)
 * Version 2.5
 * Fixed IPI issue for x1gen1 on propagation of 62.5Mhz FREQ_HZ parameter for input clocks obtained during upgrade from older versions.
 * Added support for Kintex7 Low voltage (0.9v) variants, for only Gen1 speed.
 * Removed unused Virtex6 and Spartan6 primitives.
 * Added support for kintex7 Defense grade Low voltage (0.9v) variants, for only Gen1 speed.
 * Fixed CPLL power spike on power up issue (AR 59294)
AXI Memory Mapped to Stream Mapper (1.1)
 * Version 1.1 (Rev. 2)
 * No changes
AXI Performance Monitor (5.0)
 * Version 5.0 (Rev. 4)
 * Enhanced support for IP Integrator.
 * Issue of handling metric calculation when write issuance and address issuance are very close is fixed.
 * Added support for asynchronous Reset event and capture events.
AXI Protocol Checker (1.1)
 * Version 1.1 (Rev. 4)
 * Updated IP integrator automation to latest API, no functional changes
AXI Protocol Converter (2.1)
 * Version 2.1 (Rev. 3)
 * Clean-up benign Multiple Driver Nets warnings
AXI Quad SPI (3.2)
 * Version 3.2 (Rev. 2)
 * Improved GUI speed and responsiveness.
 * IP modified to improve the performance.
 * IP modified to use new sub-cores in place of proc_common.
 * Numonyx Flash is renamed to Micron(Numonyx) in GUI.
 * No Functional changes.
 * Updating core to use utils.tcl needed for board flow from common location
 * Disabled STARTUP block support in UltraScale devices.
AXI Register Slice (2.1)
 * Version 2.1 (Rev. 3)
 * Repackaged REG_* user parameters to improve internal automation, no functional changes.
AXI TFT Controller (2.0)
 * Version 2.0 (Rev. 6)
 * Fixed Timing DRC in example design.
 * Updated the RTL to use new sub-cores in place of proc_common.
 * No functional changes.
AXI Timebase Watchdog Timer (2.0)
 * Version 2.0 (Rev. 6)
 * Modified to use new sub-cores in place of proc_common,no functional changes
AXI Timer (2.0)
 * Version 2.0 (Rev. 6)
 * Modified to use new sub-cores in place of proc_common,no functional changes.
AXI Traffic Generator (2.0)
 * Version 2.0 (Rev. 4)
 * Paramram support for data widths greater than 64
 * Enabled Address sweep for Static and HLTP modes.
 * Added HIGH Address parameter in Static mode and Enable sweep parameters.
 * modified to use new sub-cores in place of proc_common. No Functional changes.
 * Added logic to synchronize the external start/stop signals to s_axi_aclk clock domain. No Functional changes.
AXI UART16550 (2.0)
 * Version 2.0 (Rev. 6)
 * axi uart16550 is modified to use new sub-cores in place of proc_common. No functional changes.
 * Updating core to use utils.tcl needed for board flow from common location
AXI USB2 Device (5.0)
 * Version 5.0 (Rev. 4)
 * IP is modified to use new sub-cores in place of proc_common, no functional changes
 * Updated HSIC_INTF interface as master as it is an IO interface, no functional changes
AXI Uartlite (2.0)
 * Version 2.0 (Rev. 6)
 * axi uartlite is modified to use new sub-cores in place of proc_common. No functional changes.
 * Updating core to use utils.tcl needed for board flow from common location
AXI Video Direct Memory Access (6.2)
 * Version 6.2 (Rev. 2)
 * Scatter gather helper files packaged as part of IP.
 * Updated the RTL to use new sub-cores in place of proc_common.
 * No functional changes.
AXI Virtual FIFO Controller (2.0)
 * Version 2.0 (Rev. 6)
 * Reordered the parameters and ports in the component declaration of the subcore.
AXI-Stream FIFO (4.1)
 * Version 4.1
 * Increased the FIFO depth support up to 128K
 * Increased the AXI4 Data Width support up to 512
 * OFFSET address of TDFD and RDFD registers are changed to 0x0000 and 0x1000 respectively for AXI4 Data Interface to support wider data width
AXI4-Stream Accelerator Adapter (2.1)
 * Version 2.1 (Rev. 2)
 * Updated GUI to combine multiple tabs into max four tabs
 
AXI4-Stream Broadcaster (1.1)
 * Version 1.1 (Rev. 3)
 * Improved GUI validation for *_REMAP parameters, no functional changes
AXI4-Stream Clock Converter (1.1)
 * Version 1.1 (Rev. 4)
 * Latest FIFO Generator constraints updated.
AXI4-Stream Combiner (1.1)
 * Version 1.1 (Rev. 2)
 * No changes
AXI4-Stream Data FIFO (1.1)
 * Version 1.1 (Rev. 4)
 * Removed aresetn synchronizer when using asynchronous mode.  Reset synchronization is handled inside fifo_generator.
 * Latest FIFO Generator constraints updated.
AXI4-Stream Data Width Converter (1.1)
 * Version 1.1 (Rev. 2)
 * No changes
AXI4-Stream Interconnect (2.1)
 * Version 2.1 (Rev. 3)
 * No changes
AXI4-Stream Protocol Checker (1.1)
 * Version 1.1 (Rev. 3)
 * Updated IP integrator automation to latest API, no functional changes
AXI4-Stream Register Slice (1.1)
 * Version 1.1 (Rev. 3)
 * Optimized to remove extra flops when there is no ready signal.
AXI4-Stream Subset Converter (1.1)
 * Version 1.1 (Rev. 3)
 * Improved syntax checking for TDATA_REMAP and TUSER_REMAP
 * Repackaged IP to improve internal automation
AXI4-Stream Switch (1.1)
 * Version 1.1 (Rev. 3)
 * No changes
AXI4-Stream to Video Out (3.0)
 * Version 3.0 (Rev. 5)
 * updated demonstration testbench, no functional changes
Accumulator (12.0)
 * Version 12.0 (Rev. 4)
 * No changes
Adder/Subtracter (12.0)
 * Version 12.0 (Rev. 4)
 * No changes
Aurora 64B66B (9.3)
 * Version 9.3
 * Added support for XA7Z030 devices
 * UltraScale GT Wizard version updated
 * Core resets separated for TX/RX_Simplex dataflow configuration
 * AXI4-LITE protocol compliant GT DRP interface with optional ports added
 * Per lane AXI4-LITE GT DRP interface supported for 7-series core
 * Added support for user configurable DRP clock and INIT clock through IP GUI
 * User selectable option enabled for GT DRP interface in IP-Integrator
 * Added support for auto-propagate to INIT and DRP clock in IPI systems.
 * Addressed CPLL power down circuit requirement for 7 series Transceivers - refer AR
 * Added support for Xilinx Evaluation platform boards
 * XDCs compliant with updated timing constraining guidelines
 * Differential INIT clock input added to UltraScale example design
 * Included GT reset staging in example design, when labtools option in GUI is disabled
 * mmcm_not_locked_out polarity changed to active high for UltraScale
 * PMA_RSV attribute setting updated for 7-Series GTH designs
Aurora 8B10B (10.3)
 * Version 10.3
 * UltraScale GT Wizard version updated
 * Added support for new UltraScale devices
 * Added support for XQ7A50 devices
 * Added support for XA7Z030 devices
 * Added support for user configurable DRP clock and INIT clock through IP GUI
 * Added C_EXAMPLE_SIMULATION parameter for post synthesis/implementation simulation speedup
 * set_max_delay constrain changed to set_false_path constrains to destination flops
 * XDCs compliant with updated timing constraining guidelines
 * Added support for Xilinx Evaluation platform boards
 * User selectable option enabled for GT DRP interface in IPI systems
 * Added support for auto propagate to INIT and DRP clock in IPI systems
 * Fixed gt_dmonitorout_out data width mismatch issue for Zynq devices
 * Differential INIT clock input added to UltraScale example design
 * Addressed CPLL power down circuit requirement for 7 series Transceivers - refer AR
 * GT startup fsms updated to be complain with 7 Series GT Wizard
 * Addressed update to GTH/GTP Production RX reset sequence implementation- refer AR
 * Parameter declaration issue with IES simulator addressed
Binary Counter (12.0)
 * Version 12.0 (Rev. 4)
 * No changes
Block Memory Generator (8.2)
 * Version 8.2 (Rev. 2)
 * Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used
 * Fixed the GUI crash in Simple Dual Port RAM
 * Added support of all write modes in Simple Dual Port RAM when ECC is not used
 * Increased the supported depth to a maximum value of 256k
CIC Compiler (4.0)
 * Version 4.0 (Rev. 5)
 * Updated USE_MULT attribute on DSP48 slices, no functional changes
 * Updated MULTSIGNIN tie-off values on DSP48 slices to avoid unisim DRC warnings, no functional changes
CORDIC (6.0)
 * Version 6.0 (Rev. 5)
 * Fix for error in C model for Square Root using Unsigned Fractional type for output widths less than half the input width.
CPRI (8.3)
 * Version 8.3
 * Updated to use version 1.4 of the UltraScale GT Wizard.
 * Added speed switching for 10.1376Gbps version of the core.
 * Added transceiver monitor interface.
 * Added watchdog timer control register.
 * Added Management Clock Rate parameter for 7 series devices.
 * Improved TX Ethernet counters to prevent the generation of runt frames.
 * The directory path to the UltraScale FPGAs Transceivers Wizard output products has been shortened.
Chroma Resampler (4.0)
 * Version 4.0 (Rev. 4)
 * No changes
Clocking Wizard (5.1)
 * Version 5.1 (Rev. 4)
 * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
 
Color Correction Matrix (6.0)
 * Version 6.0 (Rev. 5)
 * No changes
Color Filter Array Interpolation (7.0)
 * Version 7.0 (Rev. 4)
 * No changes
Complex Multiplier (6.0)
 * Version 6.0 (Rev. 5)
 * No changes
Convolution Encoder (9.0)
 * Version 9.0 (Rev. 5)
 * Synthesis warning reduction, no functional changes
DDS Compiler (6.0)
 * Version 6.0 (Rev. 6)
 * DDS_Clock_Rate maximum value limit relaxed to 1000MHz. The actual maximum achievable will be determined by configuration and device.
 * C model smoke test run_bitacc_cmodel.c updated to correctly print negative values for sine and cosine when debug is enabled.  Also removed "using namespace std" line and replaced with "std::" where necessary.
DSP48 Macro (3.0)
 * Version 3.0 (Rev. 6)
 * No changes
DUC/DDC Compiler (3.0)
 * Version 3.0 (Rev. 5)
 * Synthesis warning reduction, no functional changes
Discrete Fourier Transform (4.0)
 * Version 4.0 (Rev. 5)
 * Reduce memory consumption of C model.
DisplayPort (5.0)
 * Version 5.0
 * Updated security attributes
 * Added 32-bit GT Data width support in TX and RX to improve timing
 * Added MST support in RX
 * Added support for Q grade 7 Series devices
 * Added HDCP Interface support
Distributed Memory Generator (8.0)
 * Version 8.0 (Rev. 6)
 * Reduced warnings in synthesis, no functional changes
Divider Generator (5.1)
 * Version 5.1 (Rev. 4)
 * GUI fix. When using High Radix, changes to Latency Configuration did enable or disable Latency as expected.  No functional changes.
 
ECC (2.0)
 * Version 2.0 (Rev. 6)
 * Example design changes to use encrypted design files instead of synthesized netlsit.
Ethernet 1000BASE-X PCS/PMA or SGMII (14.3)
 * Version 14.3
 * gtwizard_ultrascale upgraded to v1_4.
 * GT updates for Series-7 transceivers.
 * Fix done for high temperature calibration failure for sgmii over lvds in Series-7 CR
 * Added 3 seconds watchdog timer which resets rx path for sgmii over lvds modes and also in case of 7 series transceiver CR
 * Soft reset provision added for sgmii over lvds CR
 * Bugfix for AutoNegotiation resetting in case of resetdone deassertion instead of pausing CR
 * Included component library in vhdl block and block wrapper CR
 * Changed BUFG to BUFH on rxoutclk for Base-X and SGMII mode without fabric elastic buffer for Series-7 CR
 * Reduced timing DRCs and warnings CR
 * Changed size of gt0_dmonitor_width depending on type of transceiver CR
 * Corrected rxpmaresetdone port in cases where it was undriven CR
Ethernet PHY MII to Reduced MII (2.0)
 * Version 2.0 (Rev. 6)
 * srl_fifo is delivered as a part of IP instead of using from proc_common subcore
 * Example design updated to add cdc between async flops, No functional changes.
 * Added Support for Board Flow.
FIFO Generator (12.0)
 * Version 12.0 (Rev. 2)
 * Added support for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
 * Added support for write data count and read data count for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
 * Added support for write data count and read data count for Common Clock Block RAM FIFO when Asymmetric Port Width option is enabled for UltraScale devices.
 * Added support for Low Latency Built-in FIFO for UltraScale devices.
FIR Compiler (7.2)
 * Version 7.2
 * Optimized Halfband filter support for UltraScale devices.
 * Super sample rate support.
 * Enhanced Hardware Oversampling specification methods. Now supports input and output sample period specification.
 * CONFIG channel behavior has been updated for the Packet Synchronization method (On Packet) following power up or reset.
Fast Fourier Transform (9.0)
 * Version 9.0 (Rev. 5)
 * Rephrasing code in hybrid butterfly sub-modules to avoid vopt error during Questa elaboration.  Functionality is unchanged.
Fixed Interval Timer (2.0)
 * Version 2.0 (Rev. 4)
 * No changes
Floating-point (7.0)
 * Version 7.0 (Rev. 6)
 * Added default values to signals in the Float-to-Fixed, Exponential and Natural Logarithm operators to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low.  Functionality is unchanged.
 * Disabled debug assertions which were written to transcript during simulation, no functional changes.
 * Fixed C model to prevent crashes that could occur on 32-bit Windows platform.
G.709 FEC Encoder/Decoder (2.1)
 * Version 2.1 (Rev. 3)
 * Statistics wrapper source HDL delivered into g709_fec_v2_1 library.
 * Improve Timing for high fan-out nets driving CE and RST inputs on LUTs
 * Adding support for qvirtex7 and qkintex7 parts.
 * Correcting changelog entries for earlier releases. This core does not support Artix, Zynq nor Low Power devices.
G.975.1 EFEC I.4 Encoder/Decoder (1.0)
 * Version 1.0 (Rev. 6)
 * Added support for qvirtex7 and qkintex7 devices
G.975.1 EFEC I.7 Encoder/Decoder (2.0)
 * Version 2.0 (Rev. 6)
 * Synthesis warning reduction, no functional changes
 * Adding support for qvirtex7 and qkintex7 parts.
Gamma Correction (7.0)
 * Version 7.0 (Rev. 5)
 * No changes
Gmii to Rgmii (3.0)
 * Version 3.0 (Rev. 3)
 * Added IO Constraints
High Speed SelectIO Wizard (1.1)
 * Version 1.1
 * Bitslip Logic for RX data alignment
 * MMCM or Global Clock Buffer support for clock input to PLLE3
 * Updated RIU interface from max 8 to max 4 per interface since one RIU connects to Upper and Lower nibble BITSLICE_CONTROL
 
IBERT 7 Series GTH (3.0)
 * Version 3.0 (Rev. 6)
 * Modified the port width of internal signals and value of some parameter for GUI
IBERT 7 Series GTP (3.0)
 * Version 3.0 (Rev. 6)
 * Modified the port width of internal signals and value of some parameter for GUI
IBERT 7 Series GTX (3.0)
 * Version 3.0 (Rev. 6)
 * Added Device Support for xq7v585trf1157-1I part
IBERT 7 Series GTZ (3.1)
 * Version 3.1 (Rev. 4)
 * Added new HDL parameters C_XSDB_PERIOD_FRC & C_XSDB_PERIOD_FRC for correct linerate calculation from XSDB master.
IBERT UltraScale GTH (1.1)
 * Version 1.1
 * Added RXOUTCLK option in GUI and non optional port optional.
 
IBERT UltraScale GTY (1.0)
 * Version 1.0
 * Native Vivado Release
ILA (Integrated Logic Analyzer) (5.0)
 * Version 5.0
 * Added AXI4 Stream monitor support. New parameter option AXI4S added to C_SLOT_0_AXI_PROTOCOL
 * Four new user parameters added to support AXI4 Stream. These are C_SLOT_0_AXIS_TDATA_WIDTH, C_SLOT_0_AXIS_TID_WIDTH, C_SLOT_0_AXIS_TUSER_WIDTH, C_SLOT_0_AXIS_TID_WIDTH
 * Updated ILA IP to use new helper libraries (ltlib_v1_0 & xsdbs_v1_0)
 * Changed C_NNUM_MONITOR_SLOTS field to read only as ILA supported only interface in AXI mode
IOModule (3.0)
 * Version 3.0
 * Corrected IO_BUS mode to define it as a master interface. The corresponding mode of connected ports or interfaces must be changed to slave to match this change.
 * Updating core to use utils.tcl needed for board flow from common location
Image Enhancement (8.0)
 * Version 8.0 (Rev. 5)
 * For image noise reduction in YCbCr 4:2:2, image edges now handled correctly for chroma video component
Interlaken (1.3)
 * Version 1.3
 * GT group selection in GUI tab-3
 * Auto filling of best and possible GT locations for the selected ILKN core in GUI tab-3
 * Packet Gen/Mon updated with burst mode
 * Licensing the ILKN core
 * BURSTSHORT values supports 64,96 and 128 only due SW limitation
 * Supporting different reference clock options for GT
Interleaver/De-interleaver (8.0)
 * Version 8.0 (Rev. 4)
 * No changes
JESD204 (6.0)
 * Version 6.0
 * Replaced GT Wizard Transceiver files with JESD204 PHY Core v1.0
 * txdata, txcharisk, rxdata, rxnotintable, rxcharisk and rxdisperr are no longer single buses but have been broken up into individual lane buses. This will affect all designs with Shared Logic in Example Design
 * Added GUI option to select whether JESD204 is driven by global clock or reference clock input
 * Added GUI options to select default values for JESD204 configuration registers
 * Added GUI option to select QPLL1 for UltraScale devices
 * Added GUI options to configure transceiver settings for 7-Series devices
 * Debug port gt*_rxpmaresetdone_out has been removed. This will affect 7-series GTH and GTP designs with Transceiver Debug enabled
 * Reset module in Support Block has been removed. All reset logic is now controlled by the JESD204 PHY core. This will affect all designs with Shared Logic in Core
 * The MMCM in the 7-Series GTP clocking module has been removed, it can now be found in the Support Block of the JESD204 PHY core. This will affect 7-Series GTP designs with Shared Logic in Core
 * Ports common_pll0_*, common_pll1_* and common_pll2_* have been renamed to common0_pll_*, common1_pll_* and common2_pll_*. This will affect all 7-Series designs.
 * Fixed issue with missing reset modules in GTHE2 for line rates where RXOUT_DIV>1 (AR 59595)
JESD204 PHY (1.0)
 * Version 1.0
 * Initial Release
JTAG to AXI Master (1.0)
 * Version 1.0 (Rev. 4)
 * Added transaction pipelining functionality. Two new parameters, WR_TXN_QUEUE_LENGTH and RD_TXN_QUEUE_LENGTH, have been added to support back to back transaction.
 * Added read/write enable/disable/reset register
 
LMB BRAM Controller (4.0)
 * Version 4.0 (Rev. 5)
 * Repackaged parameters for internal automation, no functional changes
 * Added default drivers on LMB input write signals to avoid warnings, no functional changes
LTE DL Channel Encoder (3.0)
 * Version 3.0 (Rev. 5)
 * No changes
LTE Fast Fourier Transform (2.0)
 * Version 2.0 (Rev. 5)
 * No changes
LTE PUCCH Receiver (2.0)
 * Version 2.0 (Rev. 5)
 * No changes
LTE RACH Detector (2.0)
 * Version 2.0 (Rev. 5)
 * No changes
LTE UL Channel Decoder (4.0)
 * Version 4.0 (Rev. 5)
 * No changes
Local Memory Bus (LMB) 1.0 (3.0)
 * Version 3.0 (Rev. 4)
 * No changes
Mailbox (2.1)
 * Version 2.1 (Rev. 2)
 * Updated subcore references, no functional changes
 * Made period constraints applicable when not using BRAMs to implement FIFO, corrected reset constraints, and added automation
Memory Interface Generator (MIG 7 Series) (2.2)
 * Version 2.2
 * DDR3 SDRAM, DDR2 SDRAM, RLDRAM II, LPDDR2 SDRAM, QDRIIPLUS SRAM max supported frequencies updated. See (Xilinx Answer 61853) for details."
 * Resolved (Xilinx Answer 61744) "MIG 7 Series DDR3 - ECC Multiple errors are seen in hardware when targeting Vivado 2014.2.  Errors were not seen in previous versions."
 * Resolved (Xilinx Answer 61521) "MIG 7 Series - Cannot generate data width greater than 8-bits for CPG325 packages"
 * Resolved (Xilinx Answer 60480) "MIG 7 Series - Receiving ERROR [Drc 23-20] when CLOCK_DEDICATED_ROUTE set to BACKBONE but backbone resources are not used"
 * Resolved (Xilinx Answer 60051) "MIG 7 Series DDR3 - VCS simulations fail with unresolved modules"
Memory Interface Generator (MIG) (6.0)
 * Version 6.0
 * Removal of parity bit for DDR4 interface
 * Support of x4 part for DDR3 and DDR4 interfaces
 * Support of x8 Dual Rank DIMMs for DDR3 and DDR4 interfaces
 * Removal of Burst Length8 support for RLDRAM3 x36 memory devices
 * Support of HR Bank selection for DDR3 interface
 * Added Support of XSDB and Debug for RLDRAM3 and QDRIIP interfaces
 * DDR4 memory part MT40A256M16HA-083 is replaced with new part EDY4016AABG-DR-F
MicroBlaze (9.4)
 * Version 9.4
 * Added debug enhancement: External Program Trace
 * Set default value of parameter C_EDGE_IS_POSITIVE to 1
 * Corrected issue causing exception in return instruction delay slot to be ignored in rare cases. Versions that have this issue: 9.3. Can only occur when branch target cache is enabled.
 * Avoid stall for multiple outstanding data cache write accesses followed by a single access occurring in rare cases. Versions that have this issue: 9.3. Can only occur when data cache is enabled.
 * Also allow reading SLR and SHR registers when the FPU is not enabled. Versions that have this issue: 9.3, 9.2, 9.1, 9.0, 8.50.c, 8.50.b, 8.50.a, 8.40.b, 8.40.a, 8.30.a, 8.20.b, 8.20.a, 8.10.d, 8.10.c, 8.10.b, 8.10.a. Can only occur when stack protection and area optimization is enabled and the FPU is not enabled.
MicroBlaze Debug Module (MDM) (3.2)
 * Version 3.2
 * Added support for external trace
 * Updated subcore references, no functional changes
MicroBlaze MCS (2.2)
 * Version 2.2 (Rev. 2)
 * Repackaged parameters for internal automation, no functional changes
 * Updated hardware description template to avoid locale issues, no functional changes
 * Updating core to use utils.tcl needed for board flow from common location
 * Added support for clock and reset board level constraints
Multiplier (12.0)
 * Version 12.0 (Rev. 5)
 * No changes
Multiply Adder (3.0)
 * Version 3.0 (Rev. 4)
 * No changes
Mutex (2.1)
 * Version 2.1 (Rev. 2)
 * Repackaged parameters for internal automation, no functional changes
 * Corrected XDC constraint delay values
Peak Cancellation Crest Factor Reduction (5.0)
 * Version 5.0 (Rev. 3)
 * IUS simulator supported
 * (Xilinx Answer 60855) was published in 2014.2 release to achieve a better QOR through READ_FIRST to WRITE_FIRST conversion of BRAM during implementation. This has been fixed by repackaging the XDC files as a part of core release, such that the AR above is not required.
Processor System Reset (5.0)
 * Version 5.0 (Rev. 6)
 * Modified to use new sub-cores in place of proc_common,no functional changes
 * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
 * Updated core to use utils.tcl, needed for board flow from common location
QSGMII (3.2)
 * Version 3.2 (Rev. 2)
 * Uprev of UltraScale wizard to version 1.4.
RAM-based Shift Register (12.0)
 * Version 12.0 (Rev. 4)
 * No changes
RGB to YCrCb Color-Space Converter (7.1)
 * Version 7.1 (Rev. 3)
 * Converted the No Cost License core to free core. Customers can access this core like any other free core.
RXAUI (4.2)
 * Version 4.2 (Rev. 2)
 * IBUF's have been added to the refclk_p and refclk_n inputs before the IBUFGTE2 primitive for all 7-Series devices.  These were previously inferred by the tools, so there is no change to overall logical functionality.  However, this does enable Vivado commands such as report_clock_networks to work correctly at all applicable Vivado stages
 * Updated to use the latest GT UltraScale Wizard
 * Revised the UltraScale reset logic to satisfy the minimum reset pulse width requirements for reset inputs of the UltraScale GT Wizard instantiation.
 * Revised the UltraScale reset logic to assert the Rx reset to the core when the transceivers are placed in powerdown
 * For VHDL projects, all core VHDL files are now compiled into a core specific library (rxaui_v4_2 for this core version) with the exception of the top level VHDL wrapper file for the core which remains in the default library (named xil_defaultlib unless overridden by the user).  This makes the core consistent with other Xilinx IP.  No changes to core instantiations are required in customer HDL files.
 * Input port default tie-off values for IP Integrator have been added to signal_detect and removed from signals which must be connected (for example input clock ports)
 * The directory path to the UltraScale FPGAs Transceivers Wizard output products has been shortened
Reed-Solomon Decoder (9.0)
 * Version 9.0 (Rev. 6)
 * Bugfix for demo testbench which failed to compile when only one puncture pattern was specified
 * Bugfix for demo testbench could fail with index out of range.
Reed-Solomon Encoder (9.0)
 * Version 9.0 (Rev. 5)
 * Bugfix in demonstration testbench correcting the assignment of subfields for the control channel, S_AXIS_CTRL.
S/PDIF (2.0)
 * Version 2.0 (Rev. 6)
 * Modified to use new sub-cores in place of proc_common,no functional changes
SMPTE 2022-1/2 Video over IP Receiver (2.0)
 * Version 2.0
 * Upversioned BRAM and FIFO GEN subcore
 * Registers added to get valid media and FEC packet count per channel in both primary and secondary links
 * Split merged packet count into media and fec. Added another register for the merged FEC packets
 * Fixed bug on AXI-MM wvalid waiting for wready before transaction
 * Fixed Memory collision error in playout_time_mgmt module
SMPTE 2022-1/2 Video over IP Transmitter (2.0)
 * Version 2.0
 * Upversioned BRAM and FIFO GEN subcore
 * Added register for transport stream timeout detection value
 * Added ability to configure TOS and TTL of FEC packet per channel
 * Added ability to have per channel per link VLAN configuration
SMPTE SD/HD/3G-SDI (3.0)
 * Version 3.0 (Rev. 2)
 * Added EDH multicycle path constraint in core XDC
 * Added restriction for Artix7 speed grade -1
SMPTE2022-5/6 Video over IP Receiver (4.0)
 * Version 4.0
 * Design architecture improvement
 * Support seamless switching and statistic
 * Refined core register map
 * Upversioned BRAM and FIFO_GEN subcores
 * Updated Demo test bench to support seamless switching
SMPTE2022-5/6 Video over IP Transmitter (4.0)
 * Version 4.0
 * Design architecture improvement
 * Refined core register map
 * Support seamless switching, statistic, per link per channel disable, VLAN
 * Upversioned BRAM and FIFO_GEN subcores
 * Updated Demo test bench to support seamless switching
SPI-4.2 (13.0)
 * Version 13.0 (Rev. 5)
 * Update XDC set_max_delay constraints for asynchronous clock boundaries to use the "-datapath_only" switch.
 * Update example design to add ASYNC_REG=TRUE attribute on cross clock boundaries logic.
 * Update source RTL to remove redundant logic causing multi-driven net warnings.
SelectIO Interface Wizard (5.1)
 * Version 5.1 (Rev. 3)
 * Updated example design to make use of only one external clock for bidirectional data configuration
 
Serial RapidIO Gen2 (3.2)
 * Version 3.2
 * Added 7 series GTH support (AR 54372)
 * Added UltraScale GTH support
 * Updated GTX and GTP wrappers
 * Fixed Critical warning issue due to incorrect create clock constraint in the ooc.xdc (AR 57903)
Soft Error Mitigation (4.1)
 * Version 4.1 (Rev. 2)
 * Added support for xq7a50t devices.
 * Replaced the icap_clk BUFG with BUFGCE in the example design as an example of a system-level means to delay IP start up until the clock has locked or to disable the IP in debug without modifying the bitstream.
System Cache (3.0)
 * Version 3.0 (Rev. 5)
 * No changes
System Management Wizard (1.1)
 * Version 1.1 (Rev. 1)
 * Improved GUI speed and responsiveness
 * Added ANALOG constraints on vp/vn ports
 * SIN, TRIANGLE and SQUARE stimulus generation in the range 0.1 KHz to 96 KHz. CSV file format to txt file conversion for simulation.
 
Ten Gigabit Ethernet MAC (14.0)
 * Version 14.0
 * Added new 32-Bit datapath option for the core to provide lower utilization and latency
 * MDIO Ready is now returned in both the MDIO read data register and the MDIO control register
 * Updated Statistics to correctly return an AXI slave transaction error (SLVERR) when a write access is attempted
 * Updated Statistics counters to prevent TX frames smaller than 64 bytes being counted in the 64 byte frame counter
 * Added a reset synchronizer to the AXI4-Lite reset (s_axi_aresetn) to synchronize it onto the AXI4-Lite clock (s_axi_aclk); this now allows the reset to be driven asynchronously to s_axi_aclk, matching the Product Guide description.
 * Fix for corner case where an oversized VLAN frame of size 1524 bytes would be incorrectly transmitted without XGMII error codes when the TX configuration is as follows: Jumbo frames and MTU disabled; VLAN enabled; In-band FCS enabled.
 * Updated example design Transmit FIFO to ensure that the FIFO will not hang when frame sizes larger than the FIFO memory size are sent for transmission.
 * Updated example design to add a new pattern generator and checker
 * Updated example design to add a new configuration vector/AXI4-Lite control state machine
 * Updated demonstration testbench to add BIST mode support
 * Input port default tie-off values for IP Integrator have been corrected (to be logic 1) for tx_axis_aresetn, rx_axis_aresetn, tx_dcm_locked and rx_dcm_locked
 * For VHDL projects, the top level VHDL file for the core is now compiled into the default library (named xil_defaultlib unless overridden by the user).  All other core VHDL source remains in the core specific library (ten_gig_eth_mac_v14_0 for this core version).  This makes the core consistent with other Xilinx IP.
 * Added support for Zync-7000 and 7-Series Defense-grade parts
Ten Gigabit Ethernet PCS/PMA (10GBASE-R/KR) (5.0)
 * Version 5.0
 * Added new 32-bit datapath option for the core to provide lower utilization and latency
 * Added the option to remove the RX Elastic Buffer for 32-bit UltraScale BaseR permutations to enable lower latency. XGMII_RX ports are then clocked by the rxrecclk_out port
 * Added widgets to the core GUI to allow per-core-instance Transceiver and Reference Clock placement selection for UltraScale devices
 * Made the dclk input port available in all configurations, removing the internal generation of such and allowing any period on the dclk input provided by the user. There is no longer a dclk_out output. The dclk input must come from a clock buffer. core_clk156_out can be connected to the dclk input for backward compatibility.
 * Increased default Transceiver CDR Lock wait time to 37 million UI (from 50000 UI). Requires sim_speedup_control to allow simulation (see next item).
 * Added sim_speedup_control pin to allow pre- and post-synthesis/implementation simulation speedup. Pin should be tied to constant '0' or '1' in final design. Shortens the transceiver startup time and the BaseKR Autonegotiation Break Link timer.
 * Fixed behavior on TX when PCS Loopback is selected (BaseR only). Previous behavior sent 0x00FF00FF data-type words. Corrected behavior sends 0x00FF pattern.
 * Disabled the Master Watchdog when in PCS Loopback mode
 * Added pma_pmd_type port to core to allow setting of the associated register when Shared Logic in Core is selected (BaseR only). Should be tied to a constant value.
 * Added pipeline register to the Training block coefficient interaction calculations, to ease timing. No functional change.
 * Made the core_status[1] status bit synchronous to the core clock domain. It was previous synchronous to the rxusrclk2 domain.
 * For VHDL projects, the top level VHDL file for the core is now compiled into the default library (named xil_defaultlib unless overridden by the user).  All other core VHDL source remains in the core specific library (ten_gig_eth_pcs_pma_v5_0 for this core version).  This makes the core consistent with other Xilinx IP.
 * Fixed incorrect directory location of some example design files when Shared Logic in Example Design is selected. Files moved from 'imports/<corename>/synth' to 'imports/<corename>/example_design/support'
 * The directory path to the UltraScale FPGAs Transceivers Wizard output products has been shortened
 * Input port default tie-off values for IP Integrator have been added to signal_detect and tx_fault, changed to logic 1 for reset_counter_done, and removed from the GT Quad to GT Channel clock ports (which must be connected)
 * Updated to use the latest GT UltraScale Wizard
 * Disabled -1L device support for UltraScale
 * Added support for Zync-7000 and 7-Series Defense-grade parts
Test Pattern Generator (6.0)
 * Version 6.0 (Rev. 2)
 * Fixed a problem with vtiming interface causing vertical offsets, no functional changes
Timer Sync 1588 (1.2)
 * Version 1.2 (Rev. 1)
 * lp.vhd source file edited to enable successful VCS compliation, no functional changes
 * Reduced the lower supported period of the systemtimer_clk down to 10MHz (from 40MHz)
 * Refactured the timer_sync_1588_v1_2.v file to use generate statements for optional features rather than relying purely on synthesis logic stripping.  This removes Timing-6 DRC warning messages.
 * Added two extra flip-flop stages to the timer_sync_1588_v1_2_sync_block.v clock domain crossing synchronizer to improve Mean-Time-Between-Failure (MTBF)
Tri Mode Ethernet MAC (8.3)
 * Version 8.3
 * MDIO interface made optional. Updated GUI to enable this feature. The XDC files for Block level, Clocks and Example Design have been modified to remove references to MDIO design elements when the MDIO Interface is not enabled
 * Fixed bug in MDIO read operation which was observed when the MDIO read data register is accessed immediately after the completion of MDIO read cycle
 * Fixed simulation fatal error bug which was observed when the Half Duplex Statistics counters are read when the core is generated with no Half Duplex support
 * Fixed bugs in PFC frame transmission and reception at 10/100 Mpbs line-rates.
 * Logic optimizations when the core is generated without Address Filters. Consequently updated Clock XDC file to remove set_false_path constraints which refer to objects in the optimized logic, in absence of Address Filter
 * In AXI-Lite slave attachment module, connected the AXI-Lite reset to the watchdog timer counter module to prevent propagation of Simulation Xs on the AXI-Lite Bus
 * In Clocks XDC file, the false path constraint between CPU clock and registers has been re-written to make it path-specific. As this new constraint does not refer to any clocks, it has been moved to the Block XDC file
 * Updated the Clocks XDC file to remove constraints which do not refer to the any clocks. These constraints have been moved to the Block XDC file
 * Updated the Clocks XDC file, for GMII and RGMII modes, to append the clock names used in create/generate clock constraints with instance name to make them unique. This will stop the constraints from being overwritten when multiple instances of core are used
 * Updated the Example Design XDC file, for Internal mode, to fix Vivado Timing DRC violations. AXI-Lite clock is defined using get_clocks rather than create_clocks
 * Updated the Example Design XDC file, for non GMII TriSpeed modes, to fix Vivado Timing DRC violations. Removed false path constraints which are already covered by the clock grouping constraint between GTX and MII clocks
 * Updated the Block level XDC file, for non GMII TriSpeed modes, to fix Vivado Timing DRC violations. Removed false path constraints which are already covered by the clock grouping constraint between GTX and MII clocks
 * Updated the Block level XDC file, for GMII and RGMII modes, to add a set_false_path constraint to input of reset synchronizer module
 * Updating core to use utils.tcl needed for board flow from common location
 * For UltraScale devices in GMII mode - The flops used to clock-in the RX data/control are placed in the Fabric. This is done to overcome tool limitations in meeting HOLD timing requirements at the IOBs. Updated the Block XDC file to force the flops into fabric.
 * For UltraScale devices in GMII mode - The HOLD timing requirement is relaxed on the RX and TX Interfaces. This is done to overcome tool limitations in meeting HOLD timing requirements at the IOBs. Updated the Clocks XDC file.
 * For UltraScale devices in RGMII mode - The cumulative delay on the RGMII TXC output pin, which is achieved by cascading ODELAY-IDELAY elements, has been reduced to 1 ns, as additional delay is introduced on this path by various elements in the IOBs
 * For UltraScale devices in RGMII mode - The Setup and HOLD timing requirement is relaxed on the RX and TX Interfaces. The input delay value on the RX inputs is increased to 800 ns. This is done in order to overcome tool limitations in meeting HOLD timing requirements at the IOBs. Updated the Clocks XDC file
UltraScale FPGAs Transceivers Wizard (1.4)
 * Version 1.4
 * Added several new transceiver configuration preset options
 * Added an initialization module to the example design which demonstrates interactions with the reset controller helper block that can help mitigate system-related bring-up and link loss issues
 * Removed optional port gtwiz_reset_rx_data_good_in; affects configurations which locate the reset controller helper block in the core
 * Improved performance of GTH and GTY transceivers via parameter updates
 * Improved the behavior of the reset controller helper block by holding PLL and data path resets high upon device programming, then automatically running an initial reset all sequence upon GTPOWERGOOD assertion
 * Improved the behavior of the buffer bypass controller helper blocks to eliminate the risk of reporting a completed procedure based stale TXSYNCDONE and RXSYNCDONE logic levels
 * Improved example design data integrity checking with the addition of a PRBS checker-based link status indicator, its leaky bucket implementation replacing per-cycle PRBS checker status
 * Improved transceiver configuration presets which utilize more than two quads by choosing a channel from the middle quad as the default TX and RX master channel
 * Improved load time of the Wizard customization GUI, and its responsiveness when applying transceiver configuration presets
 * Expanded the range of selectable TXOUTCLK frequencies and reduced the occurrence of core generation error code 21, reporting an unsupported programmable divider value
 * Corrected the allowed GTH maximum line rate for Kintex UltraScale devices at -2 and -1 speed grades and FBV package types
 * Fixed a bug in the reset controller helper block which incorrectly initiated TX and RX reset sequences in parallel, rather than sequentially as intended, under probabilistic conditions in hardware operation
 * Fixed a bug in the Wizard customization GUI Physical Resources tab that caused the incorrect transceiver primitive type, column, bank, or pin names to be displayed for some devices
UltraScale FPGA Gen3 Integrated Block for PCI Express (3.1)
 * Version 3.1
 * Enabled GT Wizard v1.4 by default
 * Added support for VHDL wrapper
 * Added support for VCU107 Xilinx Reference Board
 * Added support for xcvu190
 * Added mcap enablement support for xcku040 and xcvu095 devices
 * Added new device/package migration mechanism (Refer to the PG156)
VIO (Virtual Input/Output) (3.0)
 * Version 3.0 (Rev. 4)
 * activity generation bug fix
 
Video Deinterlacer (4.0)
 * Version 4.0 (Rev. 6)
 * Removed duplicated warning word for IP version upgrading.
Video In to AXI4-Stream (3.0)
 * Version 3.0 (Rev. 5)
 * updated demonstration testbench, no functional changes
Video On Screen Display (6.0)
 * Version 6.0 (Rev. 6)
 * Updated the core for re-factored proc_common and axi_lite_ipif helper libraries
Video Scaler (8.1)
 * Version 8.1 (Rev. 3)
 * No changes
Video Timing Controller (6.1)
 * Version 6.1 (Rev. 3)
 * IP modified to use new sub-cores, no functional changes
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (3.0)
 * Version 3.0 (Rev. 3)
 * Fixed CPLL Power spike on power up issue (AR59294)
Viterbi Decoder (9.1)
 * Version 9.1
 * BER count failing to count last bit in the BER block if an error is present on that bit.
XADC Wizard (3.0)
 * Version 3.0 (Rev. 5)
 * Added EXTERNAL_MUXADDR_ENABLE parameter to enable MUXADDR used for Dynamic Configuration for external mux mode
 * SIN, TRIANGLE and SQUARE stimulus generation in the range 0.1 KHz to 96 KHz. CSV file format to txt file conversion for simulation.
 
XAUI (12.1)
 * Version 12.1 (Rev. 3)
 * IBUF's have been added to the refclk_p and refclk_n inputs before the IBUFGTE2 primitive for all 7-Series devices.  These were previously inferred by the tools, so there is no change to overall logical functionality.  However, this does enable Vivado commands such as report_clock_networks to work correctly at all applicable Vivado stages
 * Updated to use the latest GT UltraScale Wizard
 * Revised the UltraScale reset logic to satisfy the minimum reset pulse width requirements for reset inputs of the UltraScale GT Wizard instantiation
 * Revised the UltraScale reset logic to assert the Rx reset to the core when the transceivers are placed in powerdown
 * For VHDL projects, all core VHDL files are now compiled into a core specific library (xaui_v12_1 for this core version) with the exception of the top level VHDL wrapper file for the core which remains in the default library (named xil_defaultlib unless overridden by the user).  This makes the core consistent with other Xilinx IP.  No changes to core instantiations are required in customer HDL files
 * Input port default tie-off values for IP Integrator have been added to signal_detect and removed from clock signals (which must be connected)
 * Fixed the example design to connect the output of the dclk BUFG clock buffer to the core (previously the dclk input was connected directly to the core)
 * The directory path to the UltraScale FPGAs Transceivers Wizard output products has been shortened
YCrCb to RGB Color-Space Converter (7.1)
 * Version 7.1 (Rev. 3)
 * Converted the No Cost License core to free core. Customer can access this core like any other free cores
ZYNQ7 Processing System (5.5)
 * Version 5.5
 * The custom time stamp unit(PTP) signals will be exposed to the Programmable Logic(PL), even when the Ethernet is routed through the MIO. For more details, please refer Zynq Technical Reference Manual (UG 585) CH No. 16.4 IEEE 1588 Time Stamping. This change enables additional optional functionality for designs with Ethernet on MIO. No changes are required for existing designs
 * Updated Trace data port width dependency to be based on Trace parameters Port width will display based on user selection
 * Updated the JTAG interface from master to slave mode. Based on Zynq Technical Reference Manual, PS boot mode supports 4 master boot mode and 2 Slave JTAG Boot mode. Prior versions of Zynq PS7 IP had PL JTAG in master mode incorrectly. The JTAG port TDO will have a buffer (OBUFT) instantiated as part of the Processing System7 IP. This change only affects designs which use PL JTAG through EMIO interface. For More details, refer chapter no.6 of Zynq Technical Reference Manual (UG 585) - Boot and Configuration
 * Added range validation for SMC cycle parameters
 * Prior versions of PS7 IP had writes to certain reserved bits of DDR IOB Buffer Control (DDRIOB_DDR_CTRL). These have been fixed to 0x0.
 
ZYNQ7 Processing System BFM (2.0)
 * Version 2.0 (Rev. 3)
 * No changes
axi_sg (4.1)
 * Version 4.1
 * AXI SG uses new proc_common libraries
interrupt_controller (3.1)
 * Version 3.0 (Rev. 2)
 * uses new helper lib
lib_bmg (1.0)
 * Version 1.0
 * Initial release
lib_cdc (1.0)
 * Version 1.0
 * Initial release
lib_fifo (1.0)
 * Version 1.0
 * initial release
lib_pkg (1.0)
 * Version 1.0
 * Initial version
lib_srl_fifo (1.0)
 * Version 1.0
 * initial version
 
AR# 62144
Date Created 09/23/2014
Last Updated 10/08/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite