Version Found: v5.0 Rev1
Version Resolved: See (Xilinx Answer 69038)
The default pinout provided by MIG UltraScale does not contain any pinout violations.
However, if pins are moved in the I/O Planner it is possible DRC violations will not be caught.
If MIG UltraScale QDRII+ designs contain pinout violations, hardware failures might occur.
Below is a list of all of the MIG UltraScale QDRII+ DRC rules the I/O Planner does not detect:
Read Data (Q) Allocation:
Read Clock (CQ/CQ#) Allocation:
Memory Clock (K/K#) Allocation:
Address/Control (A/C) Pins Allocation:
These DRC violations have been fixed in Vivado 2014.3 using MIG UltraScale v6.0 but it is possible that these violations exist for older designs which will cause DRC violations when updating IP.
These are valid violations and require all customers to re-customize and fix pinout violations.
10/06/2014 - Initial Release