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AR# 62157

Design Advisory for MIG UltraScale QDRII+ - pinout DRC violations not caught in I/O Planner


Version Found: MIG UltraScale v5.0 Rev1
Version Resolved: See (Xilinx Answer 58435)

The default pinout provided by MIG UltraScale does not contain any pinout violations.

However, if pins were moved in the I/O Planner it is possible DRC violations were not caught.

If MIG UltraScale QDRII+ designs contain pinout violations hardware failures may occur.

Below is a list of all of the MIG UltraScale QDRII+ DRC rules the I/O Planner does not detect:

Read Data (Q) Allocation:
  • All byte lanes that are used for read data of a single component must be adjacent, no skip byte lanes are allowed.
  • All of the Read Data pins of a single component should not span more than 3 consecutive byte lanes.
  • If a byte lane is used for read data, Bit[0] and Bit[6] must be used.
    Read clock (CQ or CQ#) gets the first priority and data (Q) is the next since CQCQ# must be allocated to either Bit[0] or Bit[6].

Read Clock (CQ/CQ#) Allocation:
  • Read Clock pair must be allocated in one of the byte lanes that are used for the read data of the corresponding memory component.
  • CQ/CQ# must be allocated only in the center byte lanes (byte lanes 1 and 2) because other byte lanes cannot forward the clock out for read data capture.

Memory Clock (K/K#) Allocation:
  • Memory clock should come from one of the center byte lanes (byte lanes 1 & 2).

Address/Control (A/C) Pins Allocation:
  • All A/C byte lanes should be contiguous and no skipping of byte lanes is allowed.
  • There should not be any empty byte lane or read byte lane between A/C and write data byte lanes.
    This rule applies when A/C and write data share the same bank or are allocated in adjacent banks.


These DRC violations have been fixed in Vivado 2014.3 using MIG UltraScale v6.0 but it is possible that these violations exist for older designs which will cause DRC violations when updating IP.

These are valid violations and require all customers to re-customize and fix pinout violations.

Revision History:
10/06/2014 - Initial Release

Linked Answer Records

Master Answer Records

AR# 62157
Date 03/13/2015
Status Active
Type Design Advisory
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale
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