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AR# 62171

Vivado Synthesis - Why is the address register not pulled into the block RAM when it has a feedback structure?

Description

Why is the address register not pulled into the block RAM when it has a feedback structure?

Solution

Currently the address register is not pulled into the block RAM if it has a feedback structure.

See the example below:

##############################################
 always @(posedge clk)
    begin
        if(en_addr) begin
            rd_addr <= rd_addr + 1;  <----- address has feedback over here
        end
    end
    always @(posedge clk)
    begin
        if (en) begin
              RAM[wr_addr]<=di;
        end
        do <= RAM[rd_addr];
    end
###############################################

As a temporary workaround you can use the switch below in the Tcl console before launching synthesis:

set_param synth.elaboration.rodinMoreOptions "rt::set_parameter forcePackBramAddrReg true"

This will allow you to pull in the address register to block RAM.

Starting from Vivado 2015.3, this parameter is turned on by default in Synthesis.

AR# 62171
Date Created 09/24/2014
Last Updated 10/20/2015
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Artix-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
  • More
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.3
  • Less