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AR# 62181

Hardware Debug Guide - Power and Signal Integrity Analysis and Debug with added chapters specific to Memory Interface and HSSIO (GT) hardware debug

Description

This answer record includes a debug guide for power and signal integrity board level issues. It details how to accurately measure or quantify these issues based on the failing behavior. 

It also provides best practices, checklists, and methods for resolving or mitigating different types of power or signal integrity issues.

It includes focused chapters on debugging hardware related issues with memory interfaces and high speed Serial I/O (HSSIO) interfaces.

 

This debug guide is to be used by anyone working to resolve Xilinx FPGA or SoC related signal or power integrity issues.

The material here is considered additional or supplemental to the Xilinx user guides and is not meant to replace them as such.

 

Solution

 

The debug guide attached to this answer record is structured as follows:

 

Introduction.

 

Chapter 1: Power Supplies

  • Power Supply Sequencing & Ramp Up
  • Power Supply Ripple & Noise
  • Power Supply Decoupling and filtering
  • Power Supply Debug Checklist
  • Measuring Power Supply Ripple and Noise

     

Chapter 2: Signal Integrity on Critical Nets

  • Scope probes
  • PCB probing
  • Anticipate what you expect to see
  • Signal at probe point vs die
  • Inter-Symbol Interference (ISI)

     

     

Chapter 3: Debugging SSO Noise and Cross-Talk Issues

  • SSN Debug
  • SSN Mitigation Methods
  • Board-Level Cross-Talk

     

Chapter 4: Debugging Jitter Issues

  • Period Jitter
  • Period Jitter Application
  • Cycle-to-Cycle Jitter
  • Time Interval Error (TIE)
  • Duty Cycle Distortion (DCD)

     

     

Chapter 5: Debugging Memory Interface Issues, Additional Considerations

  • Reproduce the Error
  • Isolating the Error
  • Power Supply Noise
  • Address, Command, and Control Signals
  • DQ, DQS, and DM Signals

Chapter 6: Debugging High-Speed Serial Interfaces, Additional Considerations

  • Divide and Conquer
  • Components of a SerDes Link
    • Stackup and Layout Design
    • Power Supplies
    • Reference Clock
    • Transmitter
    • Receiver
    • RCAL
  • Scope the Problem
  • Debug Sequence of the Serial Line
  • Fine Tuning of TX FIR and RZ Equalizers
  • Tools for Accurate Hardware Debug

     

     

Attachments

Associated Attachments

Name File Size File Type
Hardware_Debug_Best_Practices.pdf 3 MB PDF
AR# 62181
Date 05/26/2017
Status Active
Type General Article
Devices
  • FPGA Device Families
IP
  • MIG 7 Series
  • MIG UltraScale
  • 7 Series FPGAs Transceivers Wizard
  • UltraScale FPGA Transceiver Wizard
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