When I simulate my design containing cascaded DSP48E2 slices, I get the following DRC warning message in simulation:
Why does this occur?
I do not have any issue implementing my design and the simulation works fine and so does the design on Hardware.
Do I need to worry about this DRC warning in simulation?
Simulators have no knowledge of the placement of DSP48E2s or other cells in a design.
As a result, the simulation model in the DSP48E2 situation does not know if this cascading of DSP48E2s is expected or not.
If this is not expected, simulation may differ from the hardware implementation as these cascade wires are fixed routes on the device.
As a result, the DSP48E2 slice simulation model issues the warning above for users to check that this is indeed what they want to occur and is what they expect on Hardware.
If the message has been reviewed, and the configuration makes sense and is valid, then it is possible to ignore this warning.
In Vivado 2014.4, the DRC warning message is updated to cover a "two input SUBTRACT operation" as well.