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AR# 62183

Vivado 2014.x - cascaded DSP48E2 slices report DRC warning in simulation: [Unisim DSP48E2-7], why does this occur?

Description

When I simulate my design containing cascaded DSP48E2 slices, I get the following DRC warning message in simulation:

DRC warning : [Unisim DSP48E2-7] CARRYCASCIN can only be used in the current DSP48E2 if the previous DSP48E2 is performing a two input ADD operation or the current DSP48E2 is configured in the MAC extend opmode 7'b1001000 at 1100000.000 ns. Instance acl_compare_dt128.DSP48E2_uM
The simulation model does not know the placement of the DSP48E2 slices used, so it cannot fully confirm the above warning.
It is necessary to view the placement of the DSP48E2 slices and ensure that these warnings are not being breached

Why does this occur?

I do not have any issue implementing my design and the simulation works fine and so does the design on Hardware.

Do I need to worry about this DRC warning in simulation?


Solution

Simulators have no knowledge of the placement of DSP48E2s or other cells in a design.

As a result, the simulation model in the DSP48E2 situation does not know if this cascading of DSP48E2s is expected or not.

If this is not expected, simulation may differ from the hardware implementation as these cascade wires are fixed routes on the device.

As a result, the DSP48E2 slice simulation model issues the warning above for users to check that this is indeed what they want to occur and is what they expect on Hardware.

If the message has been reviewed, and the configuration makes sense and is valid, then it is possible to ignore this warning.


In Vivado 2014.4, the DRC warning message is updated to cover a "two input SUBTRACT operation" as well.

DRC warning : [Unisim DSP48E2-7] CARRYCASCIN can only be used in the current DSP48E2 if the previous DSP48E2 is performing a two input ADD or SUBRTACT operation or the current DSP48E2 is configured in the MAC extend opmode 7'b1001000 at 1100.000 ns. Instance acl_compare_dt128.DSP48E2_uM 
The simulation model does not know the placement of the DSP48E2 slices used, so it cannot fully confirm the above warning.
It is necessary to view the placement of the DSP48E2 slices and ensure that these warnings are not being breached

 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58895 Xilinx Simulation Solution Center - Design Assistant - Simulation Libraries - UNISIM & SIMPRIM N/A N/A
AR# 62183
Date Created 09/25/2014
Last Updated 04/14/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2013.4