We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62199

2014.3 Partial Reconfiguration - Using update_design to update a cell to blackbox causes crash


When I run the full flow from post-synthesis DCP, Vivado crashes during update_design.

Example command:

update_design -cell u_XX -black_box

Error message:

# update_design -cell u_ulpu_pr_top -black_box
WARNING: [Constraints 18-294] Collapsing instance u_ulpu_pr_top into physical block pblock_u_ulpu_pr_top in floorplan checkpoint_wd21ulpu_fpga_full
INFO: [Drc 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Abnormal program termination (11)
Please check '/XX/crash_test_1/12_par_143_6/hs_err_pid3905.log' for details
Crash information in hs_err_pidXXXX.log:
# An unexpected error has occurred (11)
/lib64/libc.so.6 [0x3b99c302d0]




This issue is fixed in the 2014.4 release of Vivado Design Suite.

The work-around is to re-load the routed DCP and continue to run update_design.

AR# 62199
Date 02/27/2015
Status Archive
Type General Article
  • Vivado Design Suite - 2014.3
Page Bookmarked