We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62208

FIR Compiler v7.2 Halfband interpolation UltraScale centre tap optimization - incorrect Convergent Rounding for multiple parallel path configurations.


For UltraScale designs using a Halfband interpolation configuration, when implementing multiple parallel paths with Convergent Rounding (odd or even), the rounded output may be incorrect.

The mid-point values will not be rounded correctly and will introduce an error of +/-1.



  • Select the "Disable_Half_Band_Centre_Tap" optimization.
    This will incur an additional DSP.
  • Implement a single parallel path per FIR Compiler instance.
  • Use an alternative rounding mode.
AR# 62208
Date 11/04/2014
Status Active
Type General Article
  • FIR Compiler
Page Bookmarked