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AR# 62215

Vivado Synthesis - Strategies for reducing run time


When using Vivado Synthesis, it is sometimes necessary to analyze or find ways to reduce the run time associated with synthesis.

This article contains several suggestions.


Some run time improvements come at the expense of quality of results. 

This is not always the case, but turning off various optimizations will improve the run time of synthesis:

  •  Use the "-quick" option.
    Running Vivado Synthesis with the -quick option will greatly reduce run time as there are little or no optimizations performed.
  •  Use the "RunTimeOptimized" directive.
    The RunTimeOptimized directive is another method of reducing the optimizations performed by Vivado Synthesis.
    The "synth_design -help" option returns the following information:

     Perform fewer timing optimizations and eliminate some RTL optimizations to reduce synthesis run time.

Increases in run time can be see when a design has large loop iterations. 

Diagnosing this can be difficult, but usually relates to the logic reported in the console before or after the point at which synthesis seems to slow.

  • To improve run time performance with large loop iterations, you can split the loops into smaller loops.
    One loop can be made into two or more depending on the necessity.
    Below is a VHDL example of changing the loop range:
REG_LENGTH : integer := 10000; --
REG_LENGTH_A : integer := 5000; -- adding two generics to split the loop iteration
REG_LENGTH_B : integer := 5000); -- adding two generics to split the loop iteration
--GEN_REGS: for I in 1 to REG_LENGTH generate -- ORIGINAL
GEN_REGS: for I in 1 to REG_LENGTH_A generate   
GEN_REGS2: for I in REG_LENGTH_A to REG_LENGTH_B generate
  • There are also suggested HDL coding styles to achieve better run time from loops. such see (Xilinx Answer 55302) 
Synthesis run time can also be affected by the processing of timing constraints.
  • Make sure there are no combinational timing loops.
    If a design contains such a loop, then the synthesis report will contain the following warning:

           WARNING: [Synth 8-295] found timing loop.

  • There are also suggested methods of speeding up constraints processing, see (Xilinx Answer 56371)
    These include applying physical constraints only in implementation, and reducing the amount of wildcards used in timing constraints.
AR# 62215
Date 03/04/2015
Status Active
Type Solution Center
  • Vivado Design Suite
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