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AR# 62292

AXI Interconnect, Crossbar - How does the AXI Interconnect round-robin arbitrate during idle periods?


How does the AXI Interconnect round-robin arbitrate during idle periods?


The round-robin arbiter in the AXI Interconnect Crossbar will always choose the lowest active and eligible slave after a reset.

Slave Interfaces (SI) are disqualified when they reach their configured Acceptance limit or when the Master Interface (MI) they are requesting to access has reached its Issuance limit.

The arbiter will then grant the next active and qualified slave interface (SI) to win arbitration, wrapping at the highest SI number back to interface 0.

The age of pending requests does not matter, only the last SI that was granted determines priority during a particular cycle.

This means that if a SI is skipped due to being idle/disqualified, it might have to wait for all other slave interfaces to be granted before its next grant, regardless of how long its AWVALID/ARVALID signal has been asserted.

Disqualified MI Exception to Round-Robin

An exception to this behavior in AXI Crossbar and Interconnect 2.1 and earlier is that on the cycle immediately following an addressed but fully-issued (and hence disqualifying) MI receiving its response, the arbiter will consider new AWVALID/ARVALID requests at a higher priority than existing requests for the next clock cycle.

If a SI asserts a new request on that particular cycle, round-robin arbitration can be violated, potentially causing starvation of all other interfaces.

This can be worked around by delaying the assertion of AWVALID/ARVALID by more than the next cycle after BVALID/RVALID so that new requests never occur on that clock cycle (such as by adding an AXI Register Slice in front of the AXI Crossbar).

Alternatively, when using the AXI Crossbar directly, increase the MI Issuance parameter to greater than the sum of all SI Acceptance values that can access the MI.

This will prevent it from ever becoming disqualifying in the first place.

This issue is not currently planned to be fixed in version 2.1.
AR# 62292
Date 11/05/2014
Status Active
Type General Article
  • AXI Interconnect
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