Version Found: MIG UltraScale v5.0
Version Resolved: See (Xilinx Answer 58435)
This is a bug in the instantiation template which is generated.
It can be fixed by manually changing the direction of signals in the component declaration.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.