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AR# 62321

MIG UltraScale DDR3/DDR4 - User Inteface ports direction incorrect in instantiation template


Version Found: MIG UltraScale v5.0
Version Resolved: See (Xilinx Answer 58435)

When a DDR3/DDR4 controller core is generated with MIG for Kintex UltraScale, the ddr3_app_addr, ddr3_app_cmd, ddr3_app_wdf_data, and ddr3_app_wdf_mask are incorrectly ported as outputs instead of inputs leading to errors like the following:

[Synth 8-358] invalid actual connected to output port 'c1_ddr3_app_wdf_mask'


This is a bug in the instantiation template which is generated.

It can be fixed by manually changing the direction of signals in the component declaration.

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 62321
Date 10/14/2014
Status Active
Type Known Issues
  • Vivado Design Suite - 2014.2
  • MIG UltraScale
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