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AR# 62321

UltraScale DDR4/DDR3 - User Inteface ports direction incorrect in instantiation template


Version Found: DDR4 v5.0, DDR3 v5.0

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

When a DDR3/DDR4 controller core is generated with MIG for Kintex UltraScale, the ddr3_app_addr, ddr3_app_cmd, ddr3_app_wdf_data, and ddr3_app_wdf_mask are incorrectly ported as outputs instead of inputs leading to errors like the following:

[Synth 8-358] invalid actual connected to output port 'c1_ddr3_app_wdf_mask'


This is a bug in the instantiation template which is generated.

It can be fixed by manually changing the direction of signals in the component declaration.

Revision History:

10/08/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 62321
Date 12/22/2017
Status Active
Type Known Issues
  • Kintex UltraScale
  • Vivado Design Suite - 2014.2
  • MIG UltraScale
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