Version Found: DDR4 v5.0, DDR3 v5.0
When a DDR3/DDR4 controller core is generated with MIG for Kintex UltraScale, the ddr3_app_addr, ddr3_app_cmd, ddr3_app_wdf_data, and ddr3_app_wdf_mask are incorrectly ported as outputs instead of inputs leading to errors like the following:
This is a bug in the instantiation template which is generated.
It can be fixed by manually changing the direction of signals in the component declaration.
10/08/2014 - Initial Release