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During example design simulation, when Initiator/Target Legacyis chosen as the Port I/O Style, the tool returns the following error message:
# ** Fatal: (vsim-3363) ./../../../srio_no_hello_msg_default_example.srcs/sources_1/ip/srio_no_hello_msg_default/synth/srio_no_hello_msg_default_block.v(945): The array length (8) of VHDL port 's_axis_iotx_tuser' does not match the width (32) of its Verilog connection (11th connection). # Time: 0 ps Iteration: 0 Instance: /srio_sim/srio_example_top_primary/srio_no_hello_msg_default_inst/inst/srio_no_hello_msg_default_block_inst/srio_gen2_v3_2_unifiedtop_inst File: ./../../../srio_no_hello_msg_default_example.srcs/sources_1/ip/srio_no_hello_msg_default/srio_gen2_v3_2/hdl/srio_gen2_v3_2_unifiedtop.vhd Line: 187 # FATAL ERROR while loading design
issue is observed when Condensed I/O is chosen as the Port I/O Style.
error message only occurs when the 'HELLO Format' option is de-selected in
the core configuration GUI.
This is a known issue which is due to be fixed in a future release of the core.
Currently, example design simulation without the "HELLO format" option is not supported.
Note: "Version Found" refers to the version where the
problem was first discovered.
The problem might also exist in earlier
versions, but no specific testing has been performed to verify earlier