We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 62400: 2014.1 Partial Reconfiguration UltraScale - Is the clock PPLOC required to be within the RM?
2014.1 Partial Reconfiguration UltraScale - Is the clock PPLOC required to be within the RM?
I have a design targeting an UltraScale device.
I am receiving the following Error when Running DRC as a precondition to the command route_design:
ERROR: [Drc 23-20] Rule violation (HDPR-17) Illegal PPLOC placement outside reconfigurable Pblock - HD.RECONFIGURABLE cell 'U_test_dut' with pin 'U_test_dut/rd_clk_wr_clk' has HD.PPLOC property assigned to tile 'XIPHY_L_X32Y120'. This tile resides outside reconfigurable Pblock 'pblock_U_test_dut' range which is illegal for Partial Reconfiguration. INFO: [Vivado_Tcl 4-198] DRC finished with 1 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado_Tcl 4-16] Error(s) found during DRC. Router not run.
Is this DRC check necessary for the clock PPLOC?
The clock PPLOC is not required to be within the RM footprint.
DRC checking on clock net PPLOCs, including HDPR-17 and postRouteDRC, should be bypassed.
This issue is fixed in the 2014.2 release of Vivado Design Suite.