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AR# 62469

2013.x/2014.x UNIMACRO - ADDSUB_MACRO behaves incorrectly in simulation when LATENCY is < 2


In my design, I instantiate an ADDSUB_MACRO, and set the generic as follows:
AREG == BREG == 0, 
When LATENCY is set to less than 2, the first output will use the last ALUMODE setting.

For example:
After ADD_SUB is changed to '0', the first output "43" remains the sum of the inputs.
However, when LATENCY is set to 2, the result is correctly toggled between ADD and SUB operations.



This is a known issue with the UNIMACRO library. 

It will be fixed in Vivado 2015.1.

As a work-around, you can instantiate the primitive DSP48E1.

AR# 62469
Date 04/07/2015
Status Active
Type General Article
  • Vivado Design Suite
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