We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62471

UltraScale FPGA Gen3 Integrated Block for PCI Express v3.1 - Timing violations when implementing 2014.2 upgraded design in 2014.3


Version Found: 3.1
Version Resolved and other known issues: (Xilinx Answer 57945)

I am implementing a Vivado 2014.2 design with the UltraScale FPGA Gen3 Integrated Block for PCI Express core in Vivado 2014.3.

The tool reports timing violations in the design.

This was not occurring in Vivado 2014.2.


To work around this issue, follow the steps below:

  • Remove the current PCIe core and replace it with a new one.
    It must be generated from the start; regeneration of the core will still give the same issue.
  • Review the constraints in the generated example design XDC file and update your XDC file accordingly.

Note: The "Version Found" column lists the version the problem was first discovered.
The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
10/10/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
57945 UltraScale FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues N/A N/A
AR# 62471
Date 10/17/2014
Status Active
Type Known Issues
Page Bookmarked