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AR# 62482

2014.3 - Vivado Synthesis - Windows OS - Tactical Patch to address a crash in Synthesis due to WARNING: [Synth 8-565] redefining clock 'clock_name'

Description

I am using Vivado Design Suite 2014.3.


If Vivado Synthesis encounters multiple create_clock constraints on the same clock port, a crash may occur when using a Windows OS with the following output:

---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
WARNING: [Synth 8-565] redefining clock 'clk_name'
info: SDC command 'set_propagated_clock' ignored 2 time(s)
INFO: Moved 2 constraints on hierarchical pins to their respective driving/loading pins
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:07:16 ; elapsed = 00:09:46 . Memory (MB): peak = 1528.137 ; gain = 1362.641
---------------------------------------------------------------------------------
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check '<project_path>/<project_name>.runs/synth_1/hs_err_pid8520.log' for details

The file hs_err_pid8520.log contains the following contents:

#
# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION)
#
Stack:
no stack trace available, please use hs_err_<pid>.dmp instead.


Solution

This issue has been resolved in the 2014.4 release, and a tactical patch has been created to address this issue in 2014.3.

Expectations with a patch: 

WARNING: [Synth 8-565] will still be issued because there are multiple overwriting create_clock constraints in the design, but a crash will not occur.

Expectations without a patch:

To work around this issue without installing a patch:


1) If the multiple overwriting create_clock constraints are due to a user constraint file:
 

a) Delete or change the name of one of the multiple clock constraints so that they are no longer identical. For example:

Change

create_clock -name CLK_25_TCXO [get_ports <clock_port>] 

to 

create_clock -name CLK_25_TCXO_new [get_ports <clock_port] 


b) Set the USED_IN_SYNTHESIS property of the user constraint file to FALSE:

set_property USED_IN_SYNTHESIS FALSE [get_files <user_constraint_file>.xdc]

2) If the multiple overwriting create_clock constraints are due to overlapping IP:


Set the IP to run in Out-Of-Context mode and to be read in after Synthesis:

set_property generate_synth_checkpoint TRUE [get_ip <ip_name>] 

and 

set_property USED_IN_SYNTHESIS FALSE [get_ip <ip_name>]


Optionally you can also right click the IP and select Out-Of-Context settings to enable OOC mode.

Implementing any of the above workarounds will successfully bypass the crash.


Attachments

Associated Attachments

Name File Size File Type
AR62482_Vivado_2014_3_win64_win32_preliminary_rev1.zip 15 MB ZIP
AR# 62482
Date Created 10/14/2014
Last Updated 10/20/2014
Status Active
Type Known Issues
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite - 2014.3