AR# 62490


UltraScale I/O - Recommended design methodology for SDR 3-state flipflops


In the UltraScale IOLOGIC there is no SDR register for the 3-state. 

What is the recommendation methodology for SDR bi-directional signals or outputs with a 3-state?


The recommended design methodology is to place a data flip-flop in the IOLOGIC (OFD by using an IOB constraint) and the 3-state flip-flop in fabric and LOC it as close as possible to the IOB. 

If there is a single flip-flop driving multiple 3-states, the flip-flop should be replicated and each individual 3-state flip-flop LOCed as close as possible to the IOB.

The maximum supported frequency is 345MHz for the SDR IOLOGIC flip-flop.


For LOCking logic in the FPGA fabric with respect to the IO-logic, be aware that they do not match as they did in previous FPGA families. 

Everything is organized following the NIBBLE/BYTE structure of the I/O. 

A BYTE is generated out of two NIBBLEs, an upper NIBBLE of 7 BITSLICES and a lower NIBBLE of 6 BITSLICES.

LOCked logic in the fabric will therefore need to jump over one SLICE every 7 and 6 SLICEs

AR# 62490
Date 02/16/2015
Status Active
Type General Article
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