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AR# 62502

2014.3 Zynq-7000 Processing System 7: How to shut down a clock PLL?

Description

I want to shut off the I/O Phase Locked Loop (PLL). 

How do I disable a PLL and change the PS UART clock source to DDR PLL?


Solution

This Answer record modifies a Zynq-7000 design to print hello world through PS UART clocked off the DDR PLL.

The below steps can be followed to shut off any PLL in Zynq which provides clock to any peripheral, and to change the clock source to another PLL:

1. Create a Zynq design to print Hello world using UART (Choose DDR PLL for all the peripherals/configuration).
    Make sure that the frequency of all PLLs are the same using the advanced clocking tab with the override clocks option enabled:
AR.png
2. Notice that by default UART is sourced by the I/O PLL.
 
3. Run the design and make sure that Hello world is printed on the terminal.
 
4. Read the UART_CLK_CTRL (0x00003F03) register, the SRCSEL bits should be 0x00 (I/O PLL)
 
5. Now shut off the I/O PLL and verify that the UART no longer responds.
 
6. Write 0x00000012 to the register IO_PLL_CTRL (0xF8000108) by editing the ps7_init.tcl and/or ps7_init.c files.
 
a. The above value corresponds with a PLL_BYPASS_FORCE bit to 1,  PLL_BYPASS_QUAL bit to 0, and PLL_PWRDWN bit to 1
b. Make sure to update this to the correct procedure for the version of silicon used (For example ps7_pll_init_data_3_0 for ps7_init.tcl for production silicon)
c. In case of an FSBL flow, modify this register in the ps7_init.c file.
 
7. Run the application, UART should not print the intended string on the terminal.
 
8. Read the PLL_STATUS (0xF800010C) register, the I/O PLL should be in a "not locked" status.
 
9. Now change the UART clock source to DDR PLL.
 
10. Set SRCSEL bits to 11 of the register UART_CLK_CTRL (0xF8000154) in ps7_init.tcl or in ps7_init.c
 
a. The above value denotes UART clock source is DDR PLL.
b. Make sure to update this to the correct procedure for the version of silicon used (For example ps7_pll_init_data_3_0 for ps7_init.tcl)
c. In case of FSBL flow modify this register in ps7_init.c
 
11. Run the application, UART should print the intended string on the terminal.
AR# 62502
Date Created 10/15/2014
Last Updated 11/18/2014
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • Vivado Design Suite - 2014.3
IP
  • Processing System 7