AR# 62504


Sysgen 2014.3- Vivado Viewer issues seen in 2014.3


Some known issues have been found when using the Xilinx Viewer capability within Vivado Sysgen 2014.3 on multi-clock domain designs.

  1. The Xilinx Viewer has been seen to hang when trying to view signals from different clocks domain in the design.
    The signals in one clock domain can be selected and no issue is seen viewing those signals, however, when you add a signal from the second clock domain and re-simulate the model, the Xilinx Viewer can hang and never display the signals or the viewer.
    In order to get out of this situation both the Matlab and Vivado processes must be killed.
  2. In other situations it has been seen that when signals are added from more than one clock domain in the design to the Xilinx Viewer, the signals are not displayed correctly when the Viewer opens.
    There is no issue when individual clock domains are viewed but combining them causes problems.




It is expected that the issues described above are connected and CRs have been filed to have these issues resolved in Vivado Sysgen 2014.4.

AR# 62504
Date 11/17/2014
Status Active
Type General Article
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