Version Found: RLDRAM3 v6.0
Version Resolved: See (Xilinx Answer 69037)
The default bank and byte selection for a MIG UltraScale RLDRAM3 72-bit design fails to select all data byte lanes which prevents the IP core from being generated.
To work around this issue, the remaining data byte lanes must be manually assigned to a bank and byte lane before the IP core can be successfully generated.
10/23/2014 - Initial Release