AR# 62615

MIG 7 Series DDR3 (IPI Flow ONLY) - Warning message generated upon IPI Upgrade - Clocking structure for MIG has been updated


Version Found: MIG 7 Series v2.3

A warning message similar to the following can be generated when upgrading a MIG 7 Series IP within a Vivado 2014.4 IPI block design that includes the usage of the additional MMCM output clocks:

[ 0] design_1_mig_7series_0_0:  Clocking structure for MIG has been updated.

Additional Clkout0 value 100.000 MHz cannot be generated using the new specification.

Updated IP will use the nearest possible value of 99.279 MHz. Refer to AR62615 for more details.


This warning message is generated due to MMCM VCO frequency changes that were made along with the write calibration updates in MIG 7 Series v2.3.  

A part of the write calibration changes is to include MMCM precise fine phase adjustments.  

This requires M and D integer divide values. 

Therefore, the VCO frequency change and affected available MMCM parameters can affect the available MMCM output frequencies.

Please see (Xilinx Answer 62368) for full details on the write calibration changes. 

To work around this, select the closest clock frequency available in the MIG 7 Series GUI.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A

Associated Answer Records

AR# 62615
Date 11/24/2014
Status Active
Type Known Issues