The MIG UltraScale GUI allows core generation with invalid Bank/Byte selection (for example where Addr/Cntrl-2 is left unassigned) which can lead to placer errors such as the following:
[Place 30-687] Expected cell DDR4_1/inst/u_ddr4_mem_intfc/u_ddr4_phy/u_ddr_xiphy/byte_num.xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER.GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice be placed along with its associated I/O. Please check if the cell is properly connected to any I/O.
To ensure valid Bank and Byte selection, open the MIG I/O Planner and run "Report DRC".
If no DRC errors are detected in the I/O Planner then proceed with IP core generation.