[Place 30-687] Expected cell DDR4_1/inst/u_ddr4_mem_intfc/u_ddr4_phy/u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice be placed along with its associated I/O.
Please check if the cell is properly connected to any I/O.
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
58435 | MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions | N/A | N/A |
AR# 62649 | |
---|---|
Date | 11/05/2014 |
Status | Active |
Type | Known Issues |
Devices | |
IP |