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AR# 62667

Vivado 2014.3 - Zynq PS DDRC does not set DRAM Self-Refresh Temperature (SRT) in DRAM MR2 for High Temperature Operation

Description

Zynq PS DDRC does not set DRAM Self-Refresh Temperature (SRT) in DRAM MR2 for High Temperature Operation.

This setting uses a 2x faster refresh time when the DRAM is placed in self-refresh mode.

Solution

In the register at 0XF800602C, the reg_ddrc_emr2 does not have bit 7 set when a 95C operating range has been selected.

This bit can be manually modified in the appropriate ps7_init file to use the correct value.

This issue is currently planned to be fixed starting in Vivado 2016.2.

AR# 62667
Date Created 10/31/2014
Last Updated 01/08/2016
Status Active
Type General Article
Devices
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q