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AR# 62669

UltraScale FPGA Transceivers Wizard v1.4 Revision 1 - Release Notes and Known Issues


This answer record contains the Release Notes and Known Issues for the UltraScale FPGA Transceiver Wizard v1.4 Revision 1, released with Vivado Design Suite 2014.4.


Title: Line rate and clock frequency configuration options are not currently limited by the -1L VCCINT=0.90V option.

Description: The Kintex UltraScale Architecture Data Sheet (DS892) specifies that various GTH clock frequency ranges differ between VCCINT=0.90V and VCCINT=0.95V operation for -1L speed grade devices.

This restriction is not enforced by the Wizard.

Work-around: When configuring the Wizard for a -1L speed grade device that you intend to operate at VCCINT=0.90V, consult the relevant Data Sheet for transceiver operational limits.

To Be Fixed: 2015.1

CR: 793735

Status: Resolved in 2015.1 core v1.5 Rev1

Title: Receiver termination voltage limited to FLOAT for DC coupled links.

Description: Wizard configurations which use DC link coupling must choose FLOAT for receiver termination.

This selection is available but is not currently enforced by the Wizard.

Work-around: When customizing the Wizard core instance in the GUI, select FLOAT for the Termination field in the Receiver: Advanced section of the first tab.

To Be Fixed: 2015.3

CR: 851033

Status: Resolved in 2015.3 core v1.6

Title: GTH CPLL reset disrupts TXOUTCLK in some UltraScale engineering sample devices.

Description: In GTH configurations targeting Kintex UltraScale ES1/ES2 and Virtex UltraScale ES1 engineering sample devices, resetting the CPLL will disrupt the TXOUTCLK signal, even when the CPLL is used for the RX data path and a QPLL is used for the TX data path.

This is due to the presence and operation of the CPLL calibration procedure which briefly takes control of the TXOUTCLK source during CPLL reset, regardless of which resources the CPLL clocks.

Work-around: This behavior cannot be avoided in GTH configurations targeting the affected engineering sample devices.

If runtime disruption to TXOUTCLK in response to resetting the CPLL is not tolerable in configurations where the CPLL drives only RX resources, you must reset and achieve lock on the CPLL prior to, or separately from bringing up TX resources.

Note: This limitation has been added to the UltraScale FPGAs Transceivers Wizard Product Guide (PG182) v1.6.

AR# 62669
Date 10/20/2015
Status Archive
Type Release Notes
  • UltraScale FPGA Transceiver Wizard
  • IO Interfaces