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AR# 62687

UltraScale Integrated 100 Gb/s Ethernet (CMAC) v1.3 - Vivado 2014.3 - Implementation errors regarding GT placement when shared logic is included in example design

Description

I am using the UltraScale Integrated 100 Gb/s Ethernet (CMAC) core v1.3 from Vivado 2014.3.

Implementation errors regarding GT placement are seen when shared logic is included in the example design. 

The failure is not seen if shared logic is included in the core.

Solution

This can be fixed in the cmac_*_exdes.v file.

In the DUT instantiation change the following two line of code:
 

                 .qpll0clk_in                          ({{2{qpll0outclk_out[2]}},{4{qpll0outclk_out[1]}},{4{qpll0outclk_out[0]}}}),
                 .qpll0refclk_in                    ({{2{qpll0outrefclk_out[2]}},{4{qpll0outrefclk_out[1]}},{4{qpll0outrefclk_out[0]}}}),


To:
 

                 .qpll0clk_in                          ({{4{qpll0outclk_out[2]}},{4{qpll0outclk_out[1]}},{2{qpll0outclk_out[0]}}}),
                 .qpll0refclk_in                    ({{4{qpll0outrefclk_out[2]}},{4{qpll0outrefclk_out[1]}},{2{qpll0outrefclk_out[0]}}}),

AR# 62687
Date 11/04/2014
Status Active
Type General Article
IP
  • 40G/100G Ethernet Core