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AR# 62770

Design Advisory for 7-Series Integrated Block for PCI Express / AXI Bridge for PCI Express (Vivado 2013.3 - Vivado 2014.3) - Link training issue with GTP devices

Description

The PCIe link training on GTP devices may fail occasionally.

The issue affects the following cores, generated in Vivado versions 2013.3 to 2014.3.

  • 7 Series Integrated Block for PCI Express
  • AXI Bridge for PCI Express

The affected devices are as follows:

  • All Artix-7  
  • Zynq Z-7015  




Solution

As described in (Xilinx Answer 53561) and (Xilinx Answer 53779), there is a specific RX reset sequence requirement for GTP devices.

This requirement was implemented correctly in the wrapper generated until Vivado 2013.2.

In Vivado 2013.3, the DRP clocking was changed from 125Mhz to 62.5Mhz.

This change introduced a synchronization issue between the pipe_reset module (working at 125mhz) and the drp module (working at 62.5mhz for the core configurations listed below).

This issue essentially bypassed the RX reset sequence requirements described in the above answer records, resulting in the link training issue.

  • Gen1 - x1
  • Gen2 - x1
  • Gen1 - x2
In order to resolve this issue, make the following modification in the *pipe_clock.v file.

Only the core configurations mentioned above require this change, the other configurations are not affected and do not need to be modified.

From:



//---------- Generate DCLK Buffer ----------------------------------------------
generate if (PCIE_USERCLK2_FREQ <= 3)
    //---------- Disable DCLK Buffer -----------------------
    begin : dclk_i
    assign CLK_DCLK = userclk2_1;                       // always less than 125Mhz
    end
else
    begin : dclk_i_bufg
    //---------- DCLK Buffer -------------------------------
    BUFG dclk_i
    (
        //---------- Input ---------------------------------
        .I                          (clk_125mhz),
        //---------- Output --------------------------------
        .O                          (CLK_DCLK)
    );
    end
endgenerate


To:


//---------- Generate DCLK Buffer ----------------------------------------------
generate if (PCIE_LINK_SPEED != 1)

    begin : dclk_i_bufg
    //---------- DCLK Buffer -------------------------------
    BUFG dclk_i
    (
        //---------- Input ---------------------------------
        .I                          (clk_125mhz),
        //---------- Output --------------------------------
        .O                          (CLK_DCLK)
    );
    end

else

    //---------- Disable DCLK Buffer -----------------------
    begin : dclk_i
    assign CLK_DCLK = clk_125mhz_buf;                      
    end  
endgenerate


This issue will be fixed in the Vivado 2014.4 release.

Revision History:
11/24/2014 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
53561 Design Advisory for Artix-7 FPGA GTP Transceivers: RX Reset Sequence Requirement for Production Silicon N/A N/A
AR# 62770
Date Created 11/07/2014
Last Updated 11/20/2014
Status Active
Type Design Advisory
IP
  • 7 Series Integrated Block for PCI Express (PCIe)
  • AXI PCI Express (PCIe)