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AR# 62774

MIG UltraScale - timing failures may be seen with MIG generated example design


Version Found: MIG UltraScale v6.1
Version Resolved: See (Xilinx Answer 58435)

Timing failures within the MIG UltraScale IP core might be seen when implementing the MIG generated example design.

This only affects the MIG example design as the MIG IP core uses PBLOCK constraints to ensure timing is met when implemented by itself.


If timing failures are seen, you might be able to reduce these failures by using the PBLOCK constraint from the <ip_core_name>.xdc file and applying it to the entire MIG example design. 

For example:
create_pblock pblock_mig_0
add_cells_to_pblock pblock_mig_0 -top
resize_pblock [get_pblocks pblock_mig_0] -add {SLICE_X56Y0:SLICE_X115Y59}

If timing failures are still seen after locking the entire MIG example design logic into one PBLOCK then please open a webcase with Xilinx Technical Support.

Revision History:

11/07/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 62774
Date 11/24/2014
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale