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AR# 62785: AXI Interconnect, Data FIFO - Why does the AXI Interconnect only issue 3 outstanding transactions when a width upsize occurs?
AXI Interconnect, Data FIFO - Why does the AXI Interconnect only issue 3 outstanding transactions when a width upsize occurs?
Why does the AXI Interconnect only issue 3 outstanding transactions when a 1:2 data width upsize occurs?
The AXI Interconnect PG058 document will be modified to be similar to the following:
"When the Width Converter is configured in FIFO mode, it functions as a packet-mode FIFO, as described in the AXI Data FIFO section. That means propagation of AW channel transfers get delayed until complete write data bursts are stored in the FIFO, and AR channel transfers will get delayed as the FIFO fills until there is sufficient vacancy to accept the whole read data burst. Unlike the AXI Data FIFO, a fixed number of transactions can be accommodated in the FIFO, regardless of the actual length of the bursts, due to the width conversion function being performed. The FIFO is always implemented with a depth of 512 (single BRAM block), as viewed on the wider MI interface. When configured to upsize the data width by a factor of 2, there are only 4 burst buffers implemented in the FIFO. When configured to upsize by any larger ratio, there will be 8 buffers implemented. This will limit the maximum number of transactions the Data Width Converter can issue to the number of burst buffers - 1. Furthermore, burst buffers only become free, allowing more commands to be issued, only after each data burst is completely read from the output side of the FIFO."
Workaround: When the data width converter is on the slave side of the AXI Interconnect, instantiating a standalone AXI Data Width Converter in front of the Interconnect will allow a normal FIFO to be used inside of the interconnect without an issuance limit.
The behavior is not currently planned to be changed in version 2.1.
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