This is a known issue in 2014.3 Vivado Sysgen C-Model simulation and is due to be fixed in 2014.4.
Please update to 2014.4 to avoid this issue for the DSP48 Macro block.
For the DSP48E1 block, a fix is due in the 2015.1 release.
If it not possible to upgrade to Vivado Sysgen 2014.4 or if further assistance is needed, please contact Xilinx Technical Support.
| AR# 62803 | |
|---|---|
| Date | 11/24/2014 |
| Status | Active |
| Type | General Article |
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| IP |
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