We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62826

7 Series MIG - Jitter requirment for sys_clk input


(UG586) states:


This is the system clock input for the memory interface and is typically connected to a low-jitter external clock source."

Does MIG have a maximum jitter requirement defined for the sys_clk input?


No, MIG does not specify an input jitter requirement for sys_clk.  

The only requirement is that the Maximum Input Clock Period Jitter specification for the MMCM and PLL are met, as defined in the FPGA DC and AC Switching Characteristic Datasheet.

AR# 62826
Date 01/07/2015
Status Active
Type General Article
  • MIG 7 Series
Page Bookmarked