We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62833

Zynq-7000 APSoC, GEM – How do you use RGMII via MIO in a 7Z010 device?


The PS_MIO_VREF pin is not present in 7z010 CLG225 packages.

(UG933) - Zynq APSoC PCB Design Guide indicates that it provides a reference voltage for the RGMII input receivers.
Can the Zynq Gigabit Ethernet controller be used through the MIO interface in this case?


This description of PS_MIO_VREF in UG933 is correct but incomplete.

PS_MIO_VREF is necessary only when differential signaling is used.
Also, PS_MIO_VREF is required only for the HSTL I/O standard.
Hence LVCMOS 1.8V/2.5V with fast slew I/O standard can be used with RGMII via MIO.
AR# 62833
Date 01/07/2015
Status Active
Type General Article
  • Zynq-7000