I am receiving the following clock placement error because my GCCIO pin is not in the same clock region as the MMCM it is driving.
However, the resolution indicates that it can reach the neighboring clock region which is what I am trying to do.
Why does my configuration fail?
ERROR: [Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM.
port_mem_inst/GEN_DDR_MEM_2_IF_ON.MEM_IF/inst/u_ddr4_clk_ibuf_mmcm/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y229
port_mem_inst/GEN_DDR_MEM_2_IF_ON.MEM_IF/inst/u_ddr4_clk_ibuf_mmcm/MMCM_ADDN_CLK_ENABLE.mmcme3_adv_inst (MMCME3_ADV.CLKIN1) is provisionally placed by clock placer on MMCME3_ADV_X0Y3
Resolution: A dedicated routing path between the two can be used if: (a) The global clock-capable IO (GCIO) is placed on a GCIO capable site (b) The MMCM is placed in the same clock region as the GCIO pin. If the IOB is driving multiple MMCMs, all MMCMs must be placed in the same clock region, one clock region above or one clock region below the IOB. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays. For a workaround, please insert a BUFG on the GCIO-MMCM path.