We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 62877

Vivado IP Flow - RTL project containing an EDIF file which instantiates Xilinx IP and a wrapper around the EDIF may result in Opt 31-30 black box errors


I am using Vivado Design Suite 2014.3.

A project which worked without issue in 2014.2 now produces black box errors for the Xilinx IP cores included in the EDIF produced by a 3rd party Synthesis tool.

[Opt 31-30] Blackbox my_top/my_core_i (my_top) is driving pin D of primitive cell my_top/my_top_s. This blackbox cannot be found in the existing library.

Why does this now occur?

I have done everything the same as in the 2014.2 version.


This will occur in Vivado 2014.3 and later when an EDIF netlist is wrapped by an RTL wrapper in a Vivado RTL project. 

To make this design setup work, do one of the following:

  • Use the Netlist project flow in Vivado.
    This will allow you to bring in the EDIF file as your top level module, removing the need for the wrapper file.
    Then add your Xilinx IP XCI files as design sources.

    Note: Ensure that the IPs output products have been generated prior to implementing the design.
  • Set the hierarchical sources view (HSV) to Manual update mode. 
    Right click in the HSV and select Hierarchy Update -> No Update, Manual Compile Order.

Linked Answer Records

Associated Answer Records

AR# 62877
Date 11/24/2014
Status Active
Type General Article
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.4
Page Bookmarked