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AR# 62897

Vivado 2014.3 - Opt Design Crash in Windows 7

Description

During an Implementation run, the following crash is seen in opt_design:

 

Starting DRC Task
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 4587.133 ; gain = 0.000
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check 'L:/cvs/leitch/flexframe/flex_ucip/fpga/bld_vivado_512mig_non_packet/hs_err_pid9548.log' for details
 
How can this be avoided?

Solution

This issue has been fixed for Vivado 2015.1 which is scheduled for release in April, 2015. 

Until then, one of the following methods can be used as a work-around:

 


The parameter below can be set before "opt_design". 

set_param pwropt.cacheClockInfoForPowerOpt false

This disables caching of the clock information during the block RAM power optimization stage.

However, this can potentially increase the block RAM power optimization runtime.



In a scripted non-project flow, create a post-synthesis dcp.

Close the design with "close_design", then load the check point with "open_checkpoint post_synth.dcp" before running "opt_design".



The parameter below can be used:

set_param logicopt.enablePowerLopt false

This disables the block RAM power optimization.
 

 

AR# 62897
Date Created 11/20/2014
Last Updated 01/27/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.4