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AR# 62969

2014.4 Vivado Simulator - ERROR: [USF-XSim-62] 'elaborate' step failed with error(s) in Windows platform due to large concatenation of signals


The following error occurs in elaboration and xelab.exe stops.

ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '' file for more information.

The issue is specific to Windows.

Simulation can be successfully launched in Linux for the same design.


This issue can occur in the presence of a large concatenation of signals.
For example, a large conditional expression inside an if statement, or a signal assignment statement where the right hand side of the assignment contains a concatenation of a thousand std_logic_vectors.
During elaboration, the HDL parser will traverse the concatenation and build up a huge stack frame, eventually causing stack overflow. 

A work-around is to break up this long concatenation into several smaller ones, by creating more intermediate signals.
This issue is scheduled to be fixed in 2015.1.

A tactical patch for Vivado 2014.4 is attached.


Associated Attachments

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58882 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Behavioral Simulation N/A N/A
AR# 62969
Date 03/16/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.4
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