This issue can occur in the presence of a large concatenation of signals.
For example, a large conditional expression inside an if statement, or a signal assignment statement where the right hand side of the assignment contains a concatenation of a thousand std_logic_vectors.
During elaboration, the HDL parser will traverse the concatenation and build up a huge stack frame, eventually causing stack overflow.
A work-around is to break up this long concatenation into several smaller ones, by creating more intermediate signals.
This issue is scheduled to be fixed in 2015.1.
A tactical patch for Vivado 2014.4 is attached.